Light source driver

Patent metadata

Field	Value
Publication number	US-2016119993-A1
Application number	US-201414522407-A
Country	US
Kind code	A1
Filing date	Oct 23, 2014
Priority date	Oct 23, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

Various embodiments of a light source driver are disclosed. In one embodiment, the light source driver may have a driving transistor coupled directly to at least one light source without having additional switches such that the light source driver may be operated with a low voltage supply. Optionally, the light source drivers may have a bypassing circuit configured to reduce power consumption, and peaking current generator configured to speed up the turn on time of the at least one light source. At least some of the circuits, and block diagrams disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.

First claim

We claim:

1 . A light source driver, comprising:
a power terminal and a ground terminal; a first circuit branch having at least one light source and a driving transistor connected directly to the at least one light source, the first circuit branch coupled between the power terminal and the ground terminal; and a second circuit branch having a channel length modulation cancellation circuit coupled between the power and ground terminals in parallel to the first circuit branch, the channel length modulation cancellation circuit being configured to generate a feedback signal indicative of fluctuations in a voltage difference across the power terminal and the ground terminal to the first circuit branch.

2 . The light source driver of claim 1 , wherein the driving transistor is connected directly to one of the ground terminal and the power terminal.

3 . The light source driver of claim 1 , wherein the at least one light source is connected directly to the ground terminal.

4 . The light source driver of claim 1 , wherein the driving transistor is configured to provide a driving current to the at least one light source, and wherein the light source driver comprises a bypassing circuit having a first switch configured to circumvent the driving current away from the at least one light source.

5 . The light source driver of claim 4 , wherein the bypassing circuit comprises a second switch coupled to the driving transistor, wherein the second switch is configured to control the driving transistor such that the driving current is reduced when the second switch is activated.

6 . The light source driver of claim 5 , wherein the second switch is activated when the first switch is activated.

7 . The light source driver of claim 5 , wherein the second switch is turned on approximately within a first predetermined amount of time after the first switch is turned on, and wherein the second switch is turned off within a second predetermined amount of time before the first switch is turned off, wherein each of the first and second predetermined amount of time is less than 2 ns.

8 . The light source driver of claim 1 , further comprising a biasing circuit coupled to the driving transistor and the channel length modulation cancellation circuit.

9 . The light source driver of claim 8 , wherein the channel length modulation cancellation circuit comprises a fixed current biasing portion configured to maintain a substantially fixed biasing current in the second branch.

10 . The light source driver of claim 8 , wherein the channel length modulation cancellation circuit comprises a channel length modulation detector configured to generate the feedback signal.

11 . The light source driver of claim 10 , wherein the channel length modulation detector comprises a resistor configured to detect channel length modulation.

12 . The light source driver of claim 11 , wherein the biasing circuit comprises a first common configuration portion and the channel length modulation cancellation circuit comprises a second common configuration portion, wherein the first common configuration portion of the biasing circuit is substantially similar to the second common configuration portion of the channel length modulation cancellation circuit.

13 . The light source driver of claim 12 , wherein the first common configuration portion of the biasing circuit, and the second common configuration portion of the channel length modulation cancellation circuit comprise substantially similar components arranged in a substantially similar orientation.

14 . The light source driver of claim 1 , further comprising a peak current generator configured to provide an additional driving current to the at least one light source for a predetermined time period when the at least one light source is turned on.

15 . The light source driver of claim 1 , wherein:
the channel length modulation cancellation circuit comprise a mirrored current source, a fixed current source and a channel length modulation detector; the fixed current source and the channel length modulation detector are arranged in a parallel arrangement; and the mirror current source is connected in series to the fixed current source and the channel length modulation detector.

16 . A method for cancelling channel length modulation caused by fluctuation of supply voltage, the method comprising:
providing a voltage supply through a ground terminal and a power terminal; driving at least one light source in a first circuit branch between the ground terminal and the power terminal with a driving transistor configured to provide a driving current directly to the at least one light source; sensing a channel length modulation via a channel length modulation cancellation circuit in a second circuit branch in parallel to the first circuit branch; and providing a feedback from the channel length modulation cancellation circuit to the driving transistor so as to at least partially cancel out channel length modulation effects caused by fluctuation of the voltage supply.

17 . The method of claim 16 , further comprising circumventing the driving current driving the at least one light source to a bypassing circuit arranged in parallel to the at least one light source.

18 . The method of claim 17 , further comprising switching on an additional biasing current to the driving transistor so as to reduce the driving current.

19 . The method of claim 16 , further comprising providing a peaking current to the at least one light source for a predetermined period of time when the at least one light source is turned on.

20 . A driving apparatus configured to provide a drive current, the driving apparatus comprising:
a driving transistor having a gate terminal, a source terminal and a drain terminal; a biasing circuit coupled to the gate terminal of the driving transistor; at least one light source coupled to one of the source and drain terminals; a peaking current generator coupled to the at least one light source either directly or indirectly, the peaking current generator being configured to provide a charge-up current to the at least one light source for a predetermined time period; and a channel length modulation cancellation circuit configured to detect channel length modulation so as to provide a feedback signal indicative of the channel length modulation to the gate terminal of the driving transistor.

Assignees

• Avago Technologies General Ip

Inventors

• Lee Kah Weng

Classifications

• H05B45/345

  Current stabilisation; Maintaining constant current · CPC title

• H05B33/0848 Primary

  Electricity · mapped topic

• H05B33/0884

  Electricity · mapped topic

• H05B45/397 Primary

  Current mirror circuits · CPC title

• Y02B20/30

  Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED] · CPC title