Packaged integrated circuit waveguide interface and methods thereof

Patent metadata

Field	Value
Publication number	US-2016118705-A1
Application number	US-201414521620-A
Country	US
Kind code	A1
Filing date	Oct 23, 2014
Priority date	Oct 23, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor die including an integrated circuit, the semiconductor die having a first side and a second side; a molding compound that covers the semiconductor die, the molding compound having a first side and a second side, the molding compound first side corresponding to the semiconductor die first side, and the molding compound second side corresponding to the semiconductor die second side; and a first array of conductors, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

2 . The semiconductor device of claim 1 further comprising:
a reflector interface formed at the molding compound first side, the reflector interface substantially extending around and overlapping the first waveguide interface perimeter; and
an excitation element formed at the molding compound first side, the excitation element coupled to the semiconductor die and extending past the first waveguide interface perimeter into the first waveguide interface interior.

3 . The semiconductor device of claim 1 further comprising a conductive layer formed at the molding compound second side.

4 . The semiconductor device of claim 1 further comprising:
a circuit board having a first side and a second side; and
a second array of conductors, the second array of conductors extending from the circuit board first side to the circuit board second side, the second array of conductors arranged in the circuit board to define a second waveguide interface perimeter surrounding a second waveguide interface interior.

5 . The semiconductor device of claim 4 further comprising:
an interface structure formed at the circuit board first side, the interface structure substantially extending around and overlapping the second waveguide interface perimeter; and
a coupling structure formed at the circuit board second side, the coupling structure substantially extending around and overlapping the second waveguide interface perimeter, the coupling structure defining a coupling slot over the second waveguide interface interior.

6 . The semiconductor device of claim 5 wherein the coupling structure is physically coupled to a reflector interface with an array of conductive balls.

7 . The semiconductor device of claim 5 wherein the interface structure is configured to physically couple to a waveguide.

8 . The semiconductor device of claim 1 wherein the first array of conductors comprises vias in the molding compound filled with conductive material.

9 . The semiconductor device of claim 1 wherein the first array of conductors comprises conductive studs that are covered with the molding compound.

10 . The semiconductor device of claim 1 wherein the first array of conductors comprises a conductive ring covered with the molding compound.

11 . A semiconductor device comprising:
a semiconductor die including an integrated circuit, the semiconductor die having an active side with die bonding pads and an inactive side opposite the active side; a molding compound that covers the semiconductor die, the molding compound having a first side and a second side, the molding compound first side corresponding to the semiconductor die active side, and the molding compound second side corresponding to the semiconductor die inactive side; a first array of conductors, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior; a reflector interface formed at the molding compound first side, the reflector interface substantially extending around and overlapping the first waveguide interface perimeter; an excitation element formed at the molding compound first side, the excitation element coupled to the semiconductor die and extending past the first waveguide interface perimeter to the first waveguide interface interior; a conductive layer formed over the molding compound second side; a circuit board having a first side and a second side; a second array of conductors, the second array of conductors extending from the circuit board first side to the circuit board second side, the second array of conductors arranged in the circuit board to define a second waveguide interface perimeter surrounding a second waveguide interface interior; an interface structure formed at the circuit board first side, the interface structure substantially extending around and overlapping the second waveguide interface perimeter; a coupling structure formed at the circuit board second side, the coupling structure substantially extending around and overlapping the second waveguide interface perimeter, the coupling structure defining a coupling slot over the second waveguide interface interior; and conductive material to couple the coupling structure to the reflector interface.

12 . A method for forming a semiconductor device, the method comprising:
providing a semiconductor die including an integrated circuit, the semiconductor die having a first side and a second side; covering the semiconductor die in molding compound, the molding compound having a first side and a second side, the molding compound first side corresponding to the semiconductor die first side, and the molding compound second side corresponding to the semiconductor die second side; and forming a first array of conductors in the molding compound, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

13 . The method of claim 12 further comprising:
forming a reflector interface at the molding compound first side, the reflector interface substantially extending around and overlapping the first waveguide interface perimeter; and
forming an excitation element at the molding compound first side, the excitation element coupled to the semiconductor die and extending past the first waveguide interface perimeter to the first waveguide interface interior.

14 . The method of claim 12 further comprising forming a conductive layer at the molding compound second side.

15 . The method of claim 12 further comprising:
providing a circuit board having a first side and a second side; and
forming a second array of conductors, the second array of conductors extending from the circuit board first side to the circuit board second side, the second array of conductors arranged in the circuit board to define a second waveguide interface perimeter surrounding a second waveguide interface interior.

16 . The method of claim 15 further comprising:
forming an interface structure at the circuit board first side, the interface structure substantially extending around and overlapping the second waveguide interface perimeter; and
forming a coupling structure at the circuit board second side, the coupling structure substantially extending around and overlapping the second waveguide interface perimeter, the coupling structure defining a coupling slot over the second waveguide interface interior.

17 . The method of claim 16 further comprising physically coupling the coupling s

Assignees

• Freescale Semiconductor Inc

Inventors

• Tang Jinbang
• Tracht Neil T

Classifications

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W44/248

  for antennas · CPC title