Solid phase epitaxy of 3C-SiC on Si(001)

US2016118465A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016118465-A1
Application numberUS-201514872308-A
CountryUS
Kind codeA1
Filing dateOct 1, 2015
Priority dateOct 22, 2014
Publication dateApr 28, 2016
Grant date

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Abstract

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A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C-SiC buffer layer on Si(001) comprising a porous buffer layer of 3C-SiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.

First claim

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What we claim is: 1 . A method of making a SiC buffer layer on a Si substrate, comprising: depositing an amorphous carbon layer on a Si(001) substrate; controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer; forming a deposited film; annealing the deposited film and the Si(001) substrate; and forming a SiC buffer layer on the Si(001) substrate. 2 . The method of making a SiC buffer layer on a Si substrate of claim 1 wherein the Si(001) substrate is hydrogen passivated by chemical etching using hydrofluoric acid (HF), prior to the step of depositing a carbon layer, and wherein the deposited film has a root-mean-square roughness of about 0.3 nm. 3 . The method of making a SiC buffer layer on a Si substrate of claim 2 wherein the deposited amorphous carbon film on the Si(001) substrate is annealed and wherein the step of annealing is at a temperature of from about 850° C. to about 950° C. for about 30 minutes. 4 . The method of making a SiC buffer layer on a Si substrate of claim 3 wherein the step of depositing the amorphous carbon layer on the Si(001) substrate is by magnetron sputtering of a C target at room temperature at a rate of 0.8 nm/min. 5 . The method of making a SiC buffer layer on a Si substrate of claim 4 wherein the magnetron sputtering comprises 15 sccm Ar flow, 3 mT pressure, and 100 W DC plasma power. 6 . The method of making a SiC buffer layer on a Si substrate of claim 1 wherein the step of annealing at a temperature of about 950° C. comprises a ramp rate of about 1° C./sec and pressure below 2×10 −9 Torr. 7 . The method of making a SiC buffer layer on a Si substrate of claim 1 wherein the method is via a solid state reaction. 8 . A 3C—SiC buffer layer on Si(001), comprising: a buffer layer of 3C—SiC on a Si(001) substrate; wherein the buffer layer is produced through a solid state reaction. 9 . The 3C—SiC buffer layer on Si(001) of claim 8 wherein the buffer layer of 3C—SiC is about 1-2 nm thick. 10 . The 3C—SiC buffer layer on Si(001) of claim 9 wherein the buffer layer of 3C—SiC forms at a temperature of about 850° C. to about 950° C. 11 . The 3C—SiC buffer layer on Si(001) of claim 8 wherein the buffer layer of 3C—SiC is compatible with CVD and MBE.

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What does patent US2016118465A1 cover?
A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C-SiC buffer layer on Si(001) comprising a porous buffer layer of 3C-SiC on a Si substrate wherein the…
Who is the assignee on this patent?
Li Connie H, Jernigan Glenn G, Jonker Berend T, and 3 more
What technology area does this patent fall under?
Primary CPC classification H10P14/3256. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 28 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).