Method and apparatus for writing to a magnetic tunnel junction (mtj) by applying incrementally increasing voltage level

Patent metadata

Field	Value
Publication number	US-2016118102-A1
Application number	US-201514754635-A
Country	US
Kind code	A1
Filing date	Jun 29, 2015
Priority date	Apr 7, 2010
Publication date	Apr 28, 2016
Grant date	—

Abstract

A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

First claim

What is claimed is:

1 . A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array comprising:
a. selecting a word line that is coupled to a MTJ to be written; b. applying a voltage pulse, with a voltage level of Vx, to a bit line coupled to the MTJ; c. reading the state of the MTJ after applying the voltage pulse; d. comparing the state of the read MTJ to a value in a write latch; e. determining if a desired state is written to the read MTJ; and f. if the MTJ is determined not to be written to the desired state, increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeating steps c. through f. until the MTJ is written to the desired state.

2 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 1 , wherein the desired state is the same as an in-coming data.

3 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 1 , wherein an access transistor is coupled to the MTJ and the word line is coupled to the access transistor and wherein upon writing the desired state into the MTJ, de-selecting the word line.

4 . A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array comprising:
a. selecting a word line that is coupled to a MTJ to be written; b. applying a voltage pulse. with a voltage level of Vx, to a sense line coupled to the MTJ; c. reading the state of the MTJ after applying the voltage pulse; d. comparing the state of the read MTJ to a value in a write latch; e. determining if a desired state is written to the read MTJ; and f. if the MTJ is determined not to be written to the desired state, increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeating steps c. through f. until the MTJ is written to the desired state.

5 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 4 , wherein the desired state is the same as an in-corning data.

6 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 4 , wherein an access transistor is coupled to the MTJ and the word line is coupled to the access transistor and wherein upon writing the desired state into the MTJ, de-selecting the word line.

7 . A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array comprising:
a. selecting a word line that is initially at a particular voltage level by ramping the particular voltage level up to a voltage level, Vwl, the word line being coupled to a MTJ to be written; b. while the applying a voltage pulse, with a voltage level of Vx, to a bit line coupled to the MTJ; c. reading the state of the MTJ after applying the voltage pulse; d. comparing the state of the read MTJ to a value in a write latch; e. determining if a desired state is written to the read MTJ; and f. if the MTJ is determined not to be written to the desired state, increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeating steps c. through f. until the MTJ is written to the desired state.

8 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 7 , wherein the desired state is the same as an in-coming data.

9 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 7 , wherein an access transistor is coupled to the MTJ and the word line is coupled to the access transistor and wherein upon writing the desired state into the MTJ, de-selecting the word line.

10 . A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array comprising:
a. selecting a word line that is initially at a particular voltage level by ramping the particular voltage level up to a voltage level, Vwl, the word line being coupled to a MTJ to be written; b. while the applying a voltage pulse, with a voltage level of Vx, to a sense line coupled to the MTJ: c. reading the state of the MTJ after applying the voltage pulse; d. comparing the state of the read MTJ to a value in a write latch; e. determining if a desired state is written to the read MTJ; and f. if the MTJ is determined not to be written to the desired state, increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeating steps c. through f. until the MTJ is written to the desired state.

11 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 10 wherein the desired state is the same as an in-coming data.

12 . The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 10 , wherein an access transistor is coupled to the MTJ and the word line is coupled to the access transistor and wherein upon writing the desired state into the MTJ, de-selecting the word line.

13 . A magnetic memory system of a magnetic memory array comprising:
a magnetic memory system coupled to the write latch and including at least one magnetic tunnel junction (MTJ) coupled to a bit line. the magnetic memory system further including an access transistor coupled to the at least one MTJ, the access transistor having a gate coupled to a word line, the access transistor further coupled to a sense line, the STTMRAM operable to:
upon selection of a word line that is coupled to a MTJ to be written, apply a voltage pulse. with a voltage level of Vx, to the bit line, read the state of the MTJ after applying the voltage pulse, compare the state of the read MTJ to a value in the write latch, determine if a desired state is written to the read MTJ, and if the MTJ is determined not to be written to the desired state. increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeat read, compare, and determine until the MTJ is written to the desired state.

14 . The magnetic memory system, as recited in claim 13 , wherein the magnetic memory system is made of spin-transfer torque magnetic random access memory (STTMRAM).

15 . A magnetic memory system of a magnetic memory array comprising:
a magnetic memory system coupled to the write latch and including at least one magnetic tunnel junction (MTJ) coupled to a sense line, the magnetic memory system further including an access transistor coupled to the at least one MTJ, the access transistor having a gate coupled to a word line, the access transistor further coupled to a sense line, the STTMRAM operable to:
upon selection of a word line that is coupled to a MTJ to be written, apply a voltage pulse, with a voltage level of Vx, to the bit line, read the state of the MTJ after applying the voltage pulse. compare the state of the read MTJ to a value in the write latch, determine if a desired state is written to the read MTJ, and if the MTJ is determined not to be written to the desired state, increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeat read, compare, and determine until the MTJ is written to the desired state.

16 . The magnetic memory system, as recited in claim 15 , wherein the magnetic memory system is made of spin-transfer torque magnetic random access memory (STTMRAM).

Assignees

• Abedifard Ebrahim
• Estakhri Petro
• Avalanche Technology Inc

Inventors

• Abedifard Ebrahim
• Estakhri Petro

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/5607

  using magnetic storage elements · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title