Method and apparatus for cross-core covert channel

Patent metadata

Field	Value
Publication number	US-2016117246-A1
Application number	US-201514922239-A
Country	US
Kind code	A1
Filing date	Oct 26, 2015
Priority date	Oct 27, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

Passing messages between two virtual machines that use a single multicore processor having inclusive cache includes using a cache-based covert channel. A message bit in a first machine is interpreted as a lowest level cache flush. The cache flush in the first machine clears a L1 level cache in the second machine because of the inclusiveness property of the multicore processor cache. The second machine reads its cache and records access time. If the access time is long, then the cache was previously cleared and a logical 1 was sent by the first machine. A short access time is interpreted as a logical 0 by the second machine. By sending many bits, a message can be sent from the first virtual machine to the second virtual machine via the cache-based covert channel without using non-cache memory as a covert channel.

First claim

1 . A method of passing a message between two virtual machines that use a multicore processor having an inclusive cache shared across at least two cores, the message passed using a cache-based communication channel, the method comprising:
providing a message bit from a first virtual machine to an encoder; executing a cache command at the lowest level cache of the first virtual machine if the message bit is a logical 1 and waiting a time interval if the message bit is a logical 0; reading a cache of the second virtual machine and recording an access time of the cache read; determining, at the second virtual machine, a bit value of the message bit of the first virtual machine based on the access time of the cache read of the second virtual machine; and placing the determined bit value into a register of the second virtual machine; and repeating the above with a next bit of the message until all bits of the message of the first virtual machine are determined and collected in the register of the second virtual machine; wherein the first virtual machine and the second virtual machine do not synchronize on a cache set for the cache-based communication channel, and wherein the method avoids use of non-cache shared memory and non-cache common address space as a covert channel.

2 . The method of claim 1 , wherein the step of executing the cache command at the lowest level cache of the first virtual machine comprises flushing L3 cache of the first virtual machine.

3 . The method of claim 2 , wherein flushing L3 cache flushes all levels of cache of the first virtual machine and evicts memory information from a L1 cache of the second virtual machine.

4 . The method of claim 1 , further comprising the step of performing error correction on bits of the register of the second virtual machine.

5 . The method of claim 1 , further comprising the step of displaying information conveyed by the bits of the register of the second virtual machine.

6 . The method of claim 1 , wherein the step of determining a bit value of the message bit of the first virtual machine based on the access time comprises determining the bit value to be a logical 1 if the access time exceeds a threshold value.

7 . The method of claim 1 , wherein the step of determining a bit value of the message bit of the first virtual machine based on the access time comprises determining the bit value to be a logical 0 if the access time less than a threshold value.

8 . An apparatus for passing a message between two virtual machines, the message passed using a cache-based communication channel, the apparatus comprising:
a multicore processor having an inclusive cache shared across at least two cores and hosting a first virtual machine and a second virtual machine, and wherein the first virtual machine and the second virtual machine do not agree on a cache set used for the cache-based communication channel; a first register in the first virtual machine, the first register providing a message bit to an encoder which encodes the message bit into a cache command directed to a lowest level cache of the core of the first virtual machine if the message bit is a logical 1; a first processor core of the first virtual machine, the first processor core executing the cache command if the message bit is a logical 1 and waiting a time interval if the message bit is a logical 0; a second processor core of the second virtual machine, the second processor core acting to read a cache of the second virtual machine and record an access time of the cache read, wherein the second processor core determines a bit value of the message bit of the first virtual machine based on the access time of the cache read; a second register in the second virtual machine, the second register serving to collect successive bit values determined by the second processor core; wherein the bit values in the second register represent a message passed using a cache-based communication channel of the multiprocessor core.

9 . The apparatus of claim 8 , wherein the encoder in the first virtual machine comprises the first processor core executing an algorithm that encodes a logical 1 of the message bit into a cache flush.

10 . The apparatus of claim 9 , wherein the flush of the lowest level cache flushes all levels of cache of the first virtual machine and evicts memory information from a L1 cache of the second virtual machine.

11 . The apparatus of claim 8 , wherein error correction is performed on the message in the second register.

12 . The apparatus of claim 8 , further comprising a user interface and display of the second virtual machine for displaying the message in the second register.

13 . The apparatus of claim 8 , wherein the second processor core determines a bit value to be a logical 1 if the access time exceeds a threshold value.

14 . The apparatus of claim 8 , wherein the second processor core determines a bit value to be a logical 0 if the access time is less than a threshold value.

15 . The apparatus of claim 8 , wherein the message is passed using a cache-based covert channel that avoids use of non-cache shared memory and non-cache common address space.

Assignees

• Thomson Licensing

Inventors

• Maurice Clémentine
• Heen Olivier
• Neumann Christoph
• Francillon Aurélien

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F2212/281

  Single cache · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F2212/1016

  Performance improvement · CPC title