Instructions controlling access to shared registers of a multi-threaded processor

Patent metadata

Field	Value
Publication number	US-2016117170-A1
Application number	US-201514847157-A
Country	US
Kind code	A1
Filing date	Sep 8, 2015
Priority date	Oct 28, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

First claim

What is claimed is:

1 . A computer-implemented method of facilitating control in a multi-threaded processor, said computer-implemented method comprising:
obtaining, by the multi-threaded processor, an instruction to be executed to perform an operation, the instruction being initiated by a thread of the multi-threaded processor; initiating execution, by the multi-threaded processor, of the instruction to perform the operation, the operation comprising multiple sub-operations to be performed atomically; determining whether the instruction is to continue to execute, the determining using interlocking to determine whether the instruction has atomic access to one or more registers shared by the thread and one or more other threads of the multi-threaded processor, wherein the interlocking is to control inter-thread operations; and continuing execution of the instruction based on the interlocking indicating the instruction is to execute, the continuing execution comprising performing the operation including using at least one shared register of the one or more registers shared by the thread and the one or more other threads of the multi-threaded processor to perform the operation.

2 . The computer-implemented method of claim 1 , wherein the instruction includes a lock indicator used in the interlocking.

3 . The computer-implemented method of claim 1 , wherein the determining comprises:
determining whether a lock indicator specified in the instruction is set; checking, based on the determining indicating the lock indicator is set, whether an interlock is set for one or more other instructions; setting the interlock based on the checking indicating the interlock is not set for the one or more other instructions; and proceeding with performing the operation based on setting the interlock.

4 . The computer-implemented method of claim 3 , wherein a set lock indicator in the instruction and an unset interlock for the one or more other instructions indicates the instruction has atomic access to the one or more registers.

5 . The computer-implemented method of claim 3 , further comprising resetting the interlock, based on one of a completion of the instruction or a checkpoint of the instruction.

6 . The computer-implemented method of claim 3 , wherein the determining whether the instruction is to continue further comprises rejecting the instruction based on the checking indicating the interlock is set.

7 . The computer-implemented method of claim 1 , wherein the one or more registers comprise one or more hardware registers separate from memory of the processor.

8 . The computer-implemented method of claim 1 , wherein the instruction comprises a compare and swap register instruction.

9 . The computer-implemented method of claim 1 , wherein the instruction comprises a load and AND register instruction.

10 . The computer-implemented method of claim 1 , wherein the instruction comprises a load and OR register instruction.

Assignees

• IBM

Inventors

• Biran Giora
• Busaba Fadi Y
• Erez Ophir
• Farrell Mark S
• Heller Lisa C
• Jacobi Christian
• Mesh Alexander
• Slegel Timothy J

Classifications

• G06F9/30021 Primary

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title