Control flow graph flattening device and method

US2016117153A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016117153-A1
Application numberUS-201514922155-A
CountryUS
Kind codeA1
Filing dateOct 24, 2015
Priority dateOct 24, 2014
Publication dateApr 28, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

Control Flow Graph flattening of a function of software code comprising a plurality of basic blocks having an address and at least one instruction. A processor creates a dispatcher basic block comprising instructions to look up an address in a jump table and to jump to the address, creates the jump table associating a label of each basic block with the address of the basic block, creates a coefficient array comprising diffusion function coefficients, replaces a Jump terminal instruction by a jump to the dispatcher basic block in each of the plurality of basic blocks, creates and inserts a first branch function and a second branch function, the first branch function calculating the label of a subsequent basic block based on a diffusion function for the present basic block, the second branch function calculating the diffusion function index of the subsequent basic block based on the present diffusion function index, creates and inserts a transition function into the dispatcher basic block, the transition function obtaining the address in the jump table based on at least the label of a subsequent basic block, and creates and inserts diffusion functions in the plurality of basic blocks, each diffusion function calculating a value based on at least one diffusion coefficient in the coefficient array and the label of the present basic block.

First claim

Opening claim text (preview).

1 . A method for control flow graph flattening of a function of software code, the function comprising a plurality of basic blocks each having an address and at least one instruction, the method, performed by a processor of a device, comprising: assigning a value to at least one diffusion function coefficient of a diffusion function of each of the plurality of basic blocks; calculating changes for labels and diffusion functions indices upon transitions between the plurality of basic blocks, the changes corresponding to modifications made by a linear first branch function and a linear second branch function; creating a dispatcher basic block comprising instructions to look up an address in a jump table and to jump to the address; creating the jump table associating the label of each basic block with the address of the basic block; creating a coefficient array comprising diffusion function coefficients; replacing a jump terminal instruction by a jump to the dispatcher basic block in each of the plurality of basic blocks; creating and inserting into each of the plurality of basic blocks the first branch function and the second branch function, the first branch function taking as input a result of a diffusion function in the present basic block and outputting the label of the subsequent basic block to execute, the second branch function taking as input a diffusion function index of the present basic block and outputting a diffusion function index of the subsequent basic block based; creating and inserting a transition function into the dispatcher basic block, the transition function obtaining the address in the jump table based on at least the label of the subsequent basic block; and creating and inserting diffusion functions in the plurality of basic blocks, a diffusion function inserted in the present basic block calculating a value based on at least one diffusion function coefficient dependant on the diffusion function index and the label of the present basic block. 2 . The method of claim 1 , wherein the transition function obtains the address in the jump table based on also at least one diffusion function coefficient of the subsequent basic block. 3 . The method of claim 1 , further comprising, before creating and inserting the branch functions, assigning a value to the label of each of the plurality of basic blocks. 4 . The method of claim 1 , further comprising obtaining coefficients for each of the plurality of basic blocks. 5 . A device for control flow graph flattening of a function of software code, the function comprising a plurality of basic blocks each having an address and at least one instruction, the device comprising a hardware processor configured to: assign a value to at least one diffusion function coefficient of a diffusion function of each of the plurality of basic blocks; calculate changes for labels and diffusion functions indices upon transitions between the plurality of basic blocks, the changes corresponding to modifications made by a linear first branch function and a linear second branch function; create a dispatcher basic block comprising instructions to look up an address in a jump table and to jump to the address; create the jump table associating a label of each basic block with the address of the basic block; create a coefficient array comprising diffusion function coefficients; replace a jump terminal instruction by a jump to the dispatcher basic block in each of the plurality of basic blocks; create and insert into each of the plurality of basic blocks the first branch function and the second branch function, the first branch function taking as input a result of a diffusion function in the present basic block and outputting the label of the subsequent basic block to execute, the second branch function taking as input a diffusion function index of the present basic block and outputting a diffusion function index of the subsequent basic block based; create and insert a transition function into the dispatcher basic block, the transition function obtaining the address in the jump table based on at least the label of the subsequent basic block; and create and insert diffusion functions in the plurality of basic blocks, a diffusion function inserted in the present basic block calculating a value based on at least one diffusion function coefficient dependant on the diffusion function index and the label of the present basic block; and an interface configured to output the function after control flow graph flattening. 6 . The device of claim 5 , wherein the processor is further configured to make the transition function obtain the address in the jump table based on also at least one diffusion function coefficient of the subsequent basic block. 7 . The device of claim 5 , wherein the processor is further configured to assign a value to the label of each of the plurality of basic blocks, before creating and inserting the branch functions. 8 . The device of claim 5 , wherein the processor is further configured to obtain coefficients for each of the plurality of basic blocks.

Assignees

Inventors

Classifications

  • G06F8/433Primary

    Dependency analysis; Data or control flow analysis · CPC title

  • Optimisation · CPC title

  • Conditional branch instructions · CPC title

  • G06F21/14Primary

    against software analysis or reverse engineering, e.g. by obfuscation · CPC title

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What does patent US2016117153A1 cover?
Control Flow Graph flattening of a function of software code comprising a plurality of basic blocks having an address and at least one instruction. A processor creates a dispatcher basic block comprising instructions to look up an address in a jump table and to jump to the address, creates the jump table associating a label of each basic block with the address of the basic block, creates a coef…
Who is the assignee on this patent?
Thomson Licensing
What technology area does this patent fall under?
Primary CPC classification G06F8/433. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Apr 28 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).