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US-2024422466-A1 · Dec 19, 2024 · US
US2016112796A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016112796-A1 |
| Application number | US-201514853616-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 14, 2015 |
| Priority date | Oct 20, 2014 |
| Publication date | Apr 21, 2016 |
| Grant date | — |
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An analog signal processing circuit of a microphone includes a bias circuit including a first sub-circuit which receives a signal from the microphone to output a first signal and a second sub-circuit which receives a reference voltage to output a second signal. A fully differential circuit receives the first signal and the second signal to output a fully differential signal. Each of the first sub-circuit and the second sub-circuit includes a bias sub-circuit to apply a bias voltage.
Opening claim text (preview).
What is claimed is: 1 . An analog signal processing circuit of a microphone, comprising: a bias circuit including a first sub-circuit which receives a signal from the microphone to output a first signal and a second sub-circuit which receives a reference voltage to output a second signal; and a fully differential circuit which receives the first signal and the second signal to output a fully differential signal, wherein the first sub-circuit and the second sub-circuit includes a first bias sub-circuit and a second bias sub-circuit to apply bias voltages, respectively. 2 . The analog signal processing circuit of claim 1 , wherein each of the first and second bias sub-circuits comprises two anti-parallel diode pairs. 3 . The analog signal processing circuit of claim 2 , wherein different reference voltages are applied to the anti-parallel diode pairs, respectively. 4 . The analog signal processing circuit of claim 1 , wherein the first sub-circuit comprises a first capacitor between the microphone and the first bias sub-circuit, and the second sub-circuit comprises a second capacitor between the microphone and the second bias sub-circuit. 5 . The analog signal processing circuit of claim 4 , wherein capacitance of the first capacitor is same as that of the second capacitor. 6 . The analog signal processing circuit of claim 1 , wherein the fully differential circuit comprises a fully differential amplifier and a resistive divider. 7 . The analog signal processing circuit of claim 6 , wherein the resistive divider comprises a variable resistor. 8 . The analog signal processing circuit of claim 6 , wherein the fully differential circuit comprises a first differential input stage and a second differential input stage having two input terminals, respectively, and a differential output stage having two output terminals, and the first signal is input to one input terminal of the first differential input stage, while the second signal is input to one input terminal of the second differential input stage. 9 . The analog signal processing circuit of claim 6 , wherein the resistive divider comprises a first resistive divider connected between another input terminal of a first differential input stage and one output terminal of a differential output stage, and a second resistive divider connected between another input terminal of a second differential input stage and another output terminal of the differential output stage.
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