Signal sampling timing drift compensation

Patent metadata

Field	Value
Publication number	US-2016112183-A1
Application number	US-201414518587-A
Country	US
Kind code	A1
Filing date	Oct 20, 2014
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

Method and apparatus for signal sampling timing drift compensation are provided. Raw time values or deviations between clock and data are measured and filtered to generate filtered time information, and the filtered time information is compared to an upper bound and a lower bound. If the filtered time information is outside the upper and lower bounds, then an amount of timing compensation for the clock is computed. A signal is sent to reset the clock based on the amount of timing compensation.

First claim

What is claimed is:

1 . A method of compensating for signal sampling timing drift, the method comprising:
measuring raw time values between a clock and data; filtering the measured raw time values to generate filtered time information; comparing the filtered time information to an upper bound and a lower bound; and based upon a determination that the filtered time information is outside the upper bound and the lower bound,
computing an amount of timing compensation based upon the filtered time information; and
sending a signal to reset the clock based upon the amount of timing compensation.

2 . The method of claim 1 , further comprising:
repeating the steps of
measuring raw time values between a clock and data;
filtering the measured raw time values to generate filtered time information; and
comparing the filtered time information to an upper bound and a lower bound,
after sending the signal to reset the clock based upon the amount of timing compensation.

3 . The method of claim 1 , further comprising:
based upon a determination that the filtered time information is inside the upper bound and the lower bound, repeating the steps of:
measuring raw time values between a clock and data;
filtering the measured raw time values to generate filtered time information; and
comparing the filtered time information to an upper bound and a lower bound.

4 . The method of claim 1 , wherein filtering the measured raw time values to generate filtered time information comprises removing one or more spurious time measurement values from the measured raw time values.

5 . The method of claim 1 , wherein the data comprise a plurality of data bits, each of the data bits having a predetermined length and a center in a time domain, and wherein computing the amount of timing compensation based upon the filtered time information comprises comparing the center of a respective one of the data bits to a respective one of a plurality of clock pulses.

6 . The method of claim 5 , wherein comparing the center of a respective one of the data bits to a respective one of a plurality of clock pulses comprises comparing the center of a respective one of the data bits to a clock edge of a respective one of the plurality of clock pulses.

7 . The method of claim 6 , wherein the upper bound is a time delay of a fraction of a width of a clock pulse from the center of a respective one of the data bits to the clock edge of a respective one of the plurality of clock pulses, and wherein the lower bound is a time advancement of a fraction of a width of a clock pulse from the center of a respective one of the data bits to the clock edge to a respective one of the plurality of clock pulses.

8 . The method of claim 1 , wherein sending the signal to reset the clock based upon the amount of timing compensation comprises sending a signal to set a new rising or falling edge for a new clock pulse based upon the amount of timing compensation.

9 . The method of claim 1 , wherein the filtered time information is transmitted as an analog signal having a parameter indicating a time offset between the clock and the data.

10 . The method of claim 1 , wherein the filtered time information is transmitted as a digital signal indicating a time offset between the clock and the data.

11 . A method for compensating for signal sampling timing drift, the method comprising the steps for:
measuring raw time values between a clock and data; filtering the measured raw time values to generate filtered time information; comparing the filtered time information to an upper bound and a lower bound; and based upon a determination that the filtered time information is outside the upper bound and the lower bound, performing the steps for:
computing an amount of timing compensation based upon the filtered time information; and
sending a signal to reset the clock based upon the amount of timing compensation.

12 . The method of claim 11 , further comprising the steps for:
repeating the steps for
measuring raw time values between a clock and data;
filtering the measured raw time values to generate filtered time information; and
comparing the filtered time information to an upper bound and a lower bound,
after sending the signal to reset the clock based upon the amount of timing compensation.

13 . The method of claim 11 , further comprising the steps for:
based upon a determination that the filtered time information is inside the upper bound and the lower bound, repeating the steps for:
measuring raw time values between a clock and data;
filtering the measured raw time values to generate filtered time information; and
comparing the filtered time information to an upper bound and a lower bound.

14 . The method of claim 11 , wherein the step for filtering the measured raw time values to generate filtered time information comprises the step for removing one or more spurious time measurement values from the measured raw time values.

15 . The method of claim 11 , wherein the data comprise a plurality of data bits, each of the data bits having a predetermined length and a center in a time domain, and wherein the step for computing the amount of timing compensation based upon the filtered time information comprises the step for comparing the center of a respective one of the data bits to a respective one of a plurality of clock pulses.

16 . The method of claim 15 , wherein the step for comparing the center of a respective one of the data bits to a respective one of a plurality of clock pulses comprises the step for comparing the center of a respective one of the data bits to a clock edge of a respective one of the plurality of clock pulses.

17 . The method of claim 16 , wherein the upper bound is a time delay of a fraction of a width of a clock pulse from the center of a respective one of the data bits to the clock edge of a respective one of the plurality of clock pulses, and wherein the lower bound is a time advancement of a fraction of a width of a clock pulse from the center of a respective one of the data bits to the clock edge of a respective one of the plurality of clock pulses.

18 . The method of claim 11 , wherein the step for sending the signal to reset the clock based upon the amount of timing compensation comprises the step for sending a signal to set a new rising or falling edge for a new clock pulse based upon the amount of timing compensation.

19 . The method of claim 11 , wherein the filtered time information is transmitted as an analog signal having a parameter indicating a time offset between the clock and the data.

20 . The method of claim 11 , wherein the filtered time information is transmitted as a digital signal indicating a time offset between the clock and the data.

21 . An apparatus for compensating for signal sampling timing drift, the apparatus comprising:
means for measuring raw time values between a clock and data; means for filtering the measured raw time values to generate filtered time information; means for comparing the filtered time information to an upper bound and a lower bound; means for computing an amount of timing compensation based upon the filtered time information if the filtered time information is outside the upper bound and the lower bound; and means for sending a signal to reset the clock based upon the amount of timing compensation.

22 . The apparatus of claim 21 , wherein the means for filtering the measured raw time values

Assignees

• Qualcomm Inc

Inventors

• Drop Michael
• Chun Dexter Tamio

Classifications

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title