Silicon carbide semiconductor device and method for manufacturing same

US2016111499A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016111499-A1
Application numberUS-201314778058-A
CountryUS
Kind codeA1
Filing dateMar 29, 2013
Priority dateMar 29, 2013
Publication dateApr 21, 2016
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

First claim

Opening claim text (preview).

1 . A silicon carbide semiconductor device comprising: a source region and a channel region that are disposed on an upper surface of a silicon carbide substrate; and a gate insulating film on the channel region, wherein an interface between a surface of the channel region and the gate insulating film is formed via a termination treatment layer not containing a high concentration of carbon. 2 . A silicon carbide semiconductor device comprising: a source region and a channel region that are disposed on an upper surface of a silicon carbide substrate; and a gate insulating film on the channel region, wherein a surface of the channel region includes carbon-carbon bonds, and the density thereof per unit plane is 4×10 12 cm −2 or less. 3 . The silicon carbide semiconductor device according to claim 2 , comprising an interface termination layer with a thickness of less than 1 nm at an interface between the channel region and the gate insulating film. 4 . The silicon carbide semiconductor device according to claim 2 , wherein the interface termination layer is silicon oxynitride. 5 . A method for manufacturing a silicon carbide semiconductor device including a source region and a channel region that are disposed on an upper surface of a silicon carbide substrate, and a gate insulating film on the channel region, the method comprising: a first step of thermally oxidizing surfaces of the source region and the channel region; a second step of removing carbon-carbon bonds generated at the channel region surface in the first step; a third step of forming a gate oxide film on the channel region surface by a deposition method in the second step; and a fourth step of terminating dangling bonds at an interface between the deposited gate oxide film and the channel region in an oxidizing atmosphere containing nitrogen at 1000° C. or less. 6 . The method for manufacturing the silicon carbide semiconductor device according to claim 5 , wherein the second step is vapor-phase etching using hydrogen. 7 . The method for manufacturing the silicon carbide semiconductor device according to claim 5 , wherein the oxidizing atmosphere containing nitrogen contains nitric monoxide.

Assignees

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Classifications

  • Etching of wafers, substrates or parts of devices · CPC title

  • Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

  • of Group IV semiconductors · CPC title

  • the semiconductor being silicon carbide · CPC title

  • Silicon carbide · CPC title

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What does patent US2016111499A1 cover?
A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a cryst…
Who is the assignee on this patent?
Hitachi Ltd
What technology area does this patent fall under?
Primary CPC classification H10D62/8325. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).