Thin film transistor substrate and display

Patent metadata

Field	Value
Publication number	US-2016111453-A1
Application number	US-201514880472-A
Country	US
Kind code	A1
Filing date	Oct 12, 2015
Priority date	Oct 15, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

Disclosed is a TFT substrate, including a substrate and a gate electrode thereon. A gate insulation layer over the substrate covers the gate electrode. An active layer is disposed over the gate insulation layer. An etch stop layer is disposed over the active layer and the gate insulation layer. A first opening penetrates the etch stop layer to expose a first part of the active layer. A source electrode over the etch stop layer is electrically connected to the first part of the active layer through the first opening. A first inorganic insulation layer is disposed over the source electrode and the etch stop layer. A second opening penetrates the first inorganic insulation layer and the etch stop layer to expose a second part of the active layer.

First claim

What is claimed is:

1 . A thin film transistor substrate, comprising:
a substrate; a gate electrode disposed over the substrate; a gate insulation layer disposed over the substrate and covering the gate electrode; an active layer disposed over the gate insulation layer; an etch stop layer disposed over the active layer and the gate insulation layer; a first opening penetrating the etch stop layer to expose a first part of the active layer; a source electrode disposed over the etch stop layer and electrically connected to the first part through the first opening; a first inorganic insulation layer disposed over the source electrode and the etch stop layer; a second opening penetrating the first inorganic insulation layer and the etch stop layer to expose a second part of the active layer; a barrier layer disposed over a sidewall and a bottom of the second opening and contacting the second part; an organic insulation layer disposed over the first inorganic insulation layer; a third opening penetrating the organic insulation layer to expose the barrier layer; and a transparent electrode disposed over a part of the organic insulation layer and contacting the barrier layer through the third opening.

2 . The thin film transistor substrate as claimed in claim 1 , wherein the transparent electrode over the barrier layer is a drain electrode, the transparent electrode over the part of the organic insulation layer is a pixel electrode, and the transparent electrode over a sidewall of the third opening electrically connects the drain electrode and the pixel electrode.

3 . The thin film transistor substrate as claimed in claim 1 , further comprising a second inorganic insulation layer over the organic insulation layer.

4 . The thin film transistor substrate as claimed in claim 3 , further comprising a common electrode over a part of the second inorganic insulation layer.

5 . The thin film transistor substrate as claimed in claim 3 , further comprising a common electrode disposed between the organic insulation layer and the second inorganic insulation layer, wherein the third opening further penetrates the second inorganic insulation layer, and the pixel electrode is disposed over a part of the second inorganic insulation layer.

6 . The thin film transistor substrate as claimed in claim 1 , wherein the barrier layer comprises metal, metal oxide semiconductor, or conductive metal oxide.

7 . A display, comprising:
a thin film transistor substrate, comprising:
a substrate;
a gate electrode disposed over the substrate;
a gate insulation layer disposed over the substrate and covering the gate electrode;
an active layer disposed over the gate insulation layer;
an etch stop layer disposed over the active layer and the gate insulation layer;
a first opening penetrating the etch stop layer to expose a first part of the active layer;
a source electrode disposed over the etch stop layer and electrically connected to the first part through the first opening;
a first inorganic insulation layer disposed over the source electrode and the etch stop layer;
a second opening penetrating the first inorganic insulation layer and the etch stop layer to expose a second part of the active layer;
a barrier layer disposed over a sidewall and a bottom of the second opening and contacting the second part;
an organic insulation layer disposed over the first inorganic insulation layer;
a third opening penetrating the organic insulation layer to expose the barrier layer; and
a transparent electrode disposed over a part of the organic insulation layer and contacting the barrier layer through the third opening;
an opposite substrate; and a display medium disposed between the thin film transistor substrate and the opposite substrate.

8 . The display as claimed in claim 7 , wherein the transparent electrode over the barrier layer is a drain electrode, the transparent electrode over the part of the organic insulation layer is a pixel electrode, and the transparent electrode over a sidewall of the third opening electrically connects the drain electrode and the pixel electrode.

9 . The display as claimed in claim 7 , further comprising a second inorganic insulation layer over the organic insulation layer.

10 . The display as claimed in claim 9 , further comprising a common electrode over a part of the second inorganic insulation layer.

11 . The display as claimed in claim 9 , further comprising a common electrode disposed between the organic insulation layer and the second inorganic insulation layer, wherein the third opening further penetrates the second inorganic insulation layer, and the pixel electrode is disposed over a part of the second inorganic insulation layer.

12 . The display as claimed in claim 7 , wherein the barrier layer comprises metal, metal oxide semiconductor, or conductive metal oxide.

13 . A thin film transistor substrate, comprising:
a substrate; a gate electrode disposed over the substrate; a gate insulation layer disposed over the substrate and covering the gate electrode; an active layer disposed over the gate insulation layer; an etch stop layer disposed over the active layer and the gate insulation layer; a first opening penetrating the etch stop layer to expose a first part of the active layer; a source electrode disposed over the etch stop layer and electrically connected to the first part through the first opening; a first inorganic insulation layer disposed over the source electrode and the etch stop layer; a second opening penetrating the first inorganic insulation layer and the etch stop layer to expose a second part of the active layer; a barrier layer disposed over a sidewall and a bottom of the second opening and contacting the second part; a transparent electrode disposed over a part of the first inorganic insulation layer and contacting the barrier layer.

14 . The thin film transistor substrate as claimed in claim 13 , wherein the transparent electrode over the barrier layer is a drain electrode, and the transparent electrode over the part of the first inorganic insulation layer is a pixel electrode.

15 . The thin film transistor substrate as claimed in claim 13 , wherein the barrier layer comprises metal, metal oxide semiconductor, or conductive metal oxide.

16 . The thin film transistor substrate as claimed in claim 13 , further comprising a second inorganic insulation layer over the first inorganic insulation layer and the transparent electrode.

17 . The thin film transistor substrate as claimed in claim 16 , further comprising a common electrode over a part of the second inorganic insulation layer.

18 . The thin film transistor substrate as claimed in claim 13 , further comprising a second inorganic insulation layer between the first inorganic insulation layer and the transparent electrode.

19 . The thin film transistor substrate as claimed in claim 18 , further comprising a common electrode between the first inorganic insulation layer and the second inorganic insulation layer.

20 . The thin film transistor substrate as claimed in claim 19 , wherein the barrier layer and the transparent electrode are same material.

Assignees

• Innolux Corp

Inventors

• Lee Kuan-Feng
• Yan Tzu-Min

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L29/786

  Electricity · mapped topic