Non-volatile, piezoelectronic memory based on piezoresistive strain produced by piezoelectric remanence

Patent metadata

Field	Value
Publication number	US-2016111154-A1
Application number	US-201514977752-A
Country	US
Kind code	A1
Filing date	Dec 22, 2015
Priority date	Mar 24, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A nonvolatile memory storage device includes a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric response of the FE material, wherein an electrical resistance of the PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the FE material resulting from a polarization of the FE material, such that a polarized state of the FE material results in a first resistance value of the PR material, and a depolarized state of the FE material results in a second resistance value of the PR material.

First claim

1 . A nonvolatile memory storage device, comprising:
a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric response of the FE material, wherein an electrical resistance of the PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the FE material resulting from a polarization of the FE material, such that a polarized state of the FE material results in a first resistance value of the PR material, and a depolarized state of the FE material results in a second resistance value of the PR material.

2 . The nonvolatile memory storage device of claim 1 , wherein the remanent strain of the FE material is achieved by initial application of a voltage across the FE material to result in an initial polarization D s , and thereafter by removal of the voltage to leave the FE material with a remanent polarization D r .

3 . The nonvolatile memory storage device of claim 2 , wherein the remanent strain of the FE material is removed by applying an alternating voltage of decreasing amplitude across the FE material.

4 . The nonvolatile memory storage device of claim 3 , further comprising a mechanical clamp surrounding the FE material and the PR material such that the remanent strain in the FE material results in the application of the compressive stress to the PR material, with the first resistance value of the PR material being lower than the second resistance value of the PR material.

5 . The nonvolatile memory storage device of claim 1 , wherein the FE material is disposed between first and second electrodes, and the PR material is disposed between the second electrode and a third electrode.

6 . A nonvolatile memory cell, comprising:
a storage transistor coupled to an access transistor, the storage transistor comprising a first ferroelectric (FE) material coupled with a first piezoresistive (PR) material through an inherent piezoelectric response of the first FE material, wherein an electrical resistance of the first PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the first FE material resulting from a polarization of the first FE material, such that a polarized state of the first FE material results in a first resistance value of the first PR material, and a depolarized state of the FE material results in a second resistance value of the first PR material that is higher than the first resistance value, wherein the first FE material is disposed between first and second electrodes, and the first PR material is disposed between the second electrode and a third electrode; wherein the first FE material is polarized by initial application of a voltage across the first FE material to result in an initial polarization D s , and thereafter by removal of the voltage to leave the first FE element with a remanent polarization D r and a remanent strain S r ; and wherein the first FE material is depolarized and the remanent strain removed by applying an alternating voltage of decreasing amplitude across the first FE material.

7 . The nonvolatile memory cell of claim 6 , wherein the access transistor further comprises:
a piezoelectric (PE) material coupled to a second PR material, wherein an electrical resistance of the second PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material; and the access transistor being coupled to a word line and a bit line such that activation of the word line causes the access transistor to facilitate read and write operations for the storage transistor.

8 . The nonvolatile memory cell of claim 7 , wherein for the access transistor:
the PE material is disposed between fourth and fifth electrodes; the second PR material is disposed between sixth and seventh electrodes; and the fifth and sixth electrodes are insulated from one another.

9 . The nonvolatile memory cell of claim 6 , wherein the access transistor is formed in a single stack with the storage transistor, the access transistor further comprising a second FE material mechanically coupled to and electrically insulated from the first FE material, the second FE material disposed between fourth and fifth electrodes.

10 . The nonvolatile memory cell of claim 9 , wherein the first PR material comprises Ca 2 RuO 4 .

11 . The nonvolatile memory cell of claim 9 , wherein the second FE material is depolarized for all read and write operations on the storage transistors in other word lines, and the second FE material is polarized for a read operation of the storage transistor on its own word line.

12 . The nonvolatile memory cell of claim 11 , wherein polarization of the second FE material without polarization of the first FE material results in a first compression of the PR material, and polarization of the second FE material with polarization of the first FE material results in a second compression of the PR material, such that the resistance of the PR material with the first compression is larger than the resistance of the PR material with the second compression.

Assignees

• IBM

Inventors

• Elmegreen Bruce G
• Martyna Glenn J
• Newns Dennis M
• Schrott Alejandro G

Classifications

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/22 Primary

  using ferroelectric elements · CPC title

• G11C2013/0095

  Write using strain induced by, e.g. piezoelectric, thermal effects · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title