Selective cuts to remove predicted interconnect bulging regions
US-2024419882-A1 · Dec 19, 2024 · US
System and method for obstacle-avoiding signal bus routing
US2016110490A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016110490-A1 |
| Application number | US-201414518206-A |
| Country | US |
| Kind code | A1 |
| Filing date | Oct 20, 2014 |
| Priority date | Oct 20, 2014 |
| Publication date | Apr 21, 2016 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location may be determined.
First claim
Opening claim text (preview).
What is claimed is: 1 . A computer-implemented method comprising: determining at least one candidate routing solution for routing a signal bus from a source location to a target location in a design space of an integrated circuit design representing an integrated circuit by: (i) generating, by a bus routing tool, a plurality of nodes having defined design space properties, starting with a root node proximate the source location and recursively expanding toward the target locat…
Assignees
Inventors
Classifications
- G06F30/394Primary
Physics · mapped topic
- G06F17/5077Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2016110490A1 cover?
- Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine …
- Who is the assignee on this patent?
- Oracle Int Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F30/394. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Apr 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).