Memory protection key architecture with independent user and supervisor domains

Patent metadata

Field	Value
Publication number	US-2016110298-A1
Application number	US-201414519648-A
Country	US
Kind code	A1
Filing date	Oct 21, 2014
Priority date	Oct 21, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

First claim

What is claimed is:

1 . A processing system comprising:
a processing core to execute a task; and a memory management unit, coupled to the processing core, comprising:
a storage unit to store a page table entry comprising one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode;
a first permission register comprising a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode; and
a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

2 . The processing system of claim 1 , wherein the memory management unit further comprises a multiplexer comprising a first input coupled to the first permission register, a second input coupled to the second permission register, and a control pin coupled to the access mode bit.

3 . The processing system of claim 2 , wherein the multiplexer, responsive to the access mode bit indicating the user mode, is to provide a first set of bits stored in one of the plurality of fields of the first permission register to an output of the multiplexer, and the multiplexer, responsive to the access mode bit indicating the supervisor mode, is to provide a second set of bits stored in one of the plurality of fields of the second permission register to the output of the multiplexer.

4 . The processing system of claim 3 , wherein the one of the plurality of fields of the first permission register is selected according to the protection key of the page table entry, and the one of the plurality fields of the second permission register is selected according to the protection key of the page table entry.

5 . The processing system of claim 3 , wherein the first set of bits comprises at least one of a first bit indicating a read permission, a second bit indicating a write permission, or a third bit indicating an execution permission, and wherein the second set of bits comprises at least one of a first bit indicating a read permission, a second bit indicating a write permission, or a third bit indicating an execution permission.

6 . The processing system of claim 5 , wherein the page table entry comprises a plurality of status bits.

7 . The processing system of claim 6 , wherein the memory management unit comprises a controller to receive the plurality of status bits and determine a first set of memory access permissions based on the plurality of status bits, and wherein the first set of memory access permissions comprises at least one of a first bit indicating a read permission, a second bit indicating a write permission, or a third bit indicating an execution permission.

8 . The processing system of claim 7 , wherein the memory management unit comprises an AND logic comprising a first input to receive the first of memory access permissions and a second input to receive a second set of memory access permissions from the output of the multiplexer, wherein the AND logic is to generate a set of final memory access permissions based on the first and the second sets of memory access permissions.

9 . The processing system of claim 8 , wherein the memory management unit provides the task access to the one or more memory frames based on the final memory access permission.

10 . The processing system of claim 1 , wherein the task has a privilege level of one of a user-mode access or a supervisor-mode access.

11 . The processing system of claim 10 , wherein the first permission register is accessible by the task having a privilege level of one of the user-mode access or the supervisor-mode access.

12 . The processing system of claim 11 , wherein the first permission register comprises multiple permissions bits that are settable by the task having the privilege level of one of the user-mode access or the supervisor-mode access.

13 . The processing system of claim 12 , wherein the task having the privilege level of one of the user-mode access or the supervisor-mode access is to identify a permission bit stored in the first permission register and set the permission bit to disable the permission.

14 . The processor of claim 1 , wherein the protection key comprises n bits, and each of the first and second permission registers comprises 2 n fields.

15 . A system-on-a chip (SoC) comprising:
a memory; and a processor, communicatively coupled to the memory, comprising:
a processing core to execute a task; and
a memory management unit, coupled to the processing core, comprising:
a storage unit to store a page table entry comprising one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode;
a first permission register comprising a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode; and
a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

16 . The SoC of claim 15 , wherein the memory management unit further comprises a multiplexer comprising a first input coupled to the first permission register, a second input coupled to the second permission register, and a control pin coupled to the access mode bit.

17 . The SoC of claim 16 , wherein the multiplexer, responsive to the access mode bit indicating the user mode, is to provide a first set of bits stored in one of the plurality of fields of the first permission register to an output of the multiplexer, and the multiplexer, responsive to the access mode bit indicating the supervisor mode, is to provide a second set of bits stored in one of the plurality of fields of the second permission register to the output of the multiplexer.

18 . The SoC of claim 17 , wherein the one of the plurality of fields of the first permission register is selected according to the protection key of the page table entry, and the one of the plurality fields of the second permission register is selected according to the protection key of the page table entry.

19 . The SoC of claim 17 , wherein the first set of bits comprises at least one of a first bit indicating a read permission, a second bit indicating a write permission, or a third bit indicating an execution permission, and wherein the second set of bits comprises at least one of a first bit indicating a read permission, a second bit indicating a write permission, or a third bit indicating an execution permission.

20 . The SoC of claim 19 , wherein the page table entry comprises a plurality of status bits, wherein the memory management unit comprises a controller to receive the plurality of status bits and determine a first set of memory access permissions based on the plurality of status bits, and wherein the first set of memory access permissions comprises at least one of a first bit indicating a read permission, a second bit indicating a write permission, or a third bit indicating an execution permission, and wherein the memory management unit comprises an AND logic comprising a first input to receive the first of memory access permissions and a second input to receive a second set of memory access permissions from the output of the multiplexer, wherein the AN

Assignees

• Intel Corp

Inventors

• Koufaty David A
• Neiger Gilbert
• Sankaran Rajesh M
• Anderson Andrew V
• Dulloor Subramanya R
• Haas Werner
• Nuzman Joseph

Classifications

• G06F2212/1052

  Security improvement · CPC title

• G06F12/1466 Primary

  Key-lock mechanism · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F21/6218

  to a system of files or objects, e.g. local or distributed file system or database · CPC title