Lba blocking table for ssd controller

Patent metadata

Field	Value
Publication number	US-2016110296-A1
Application number	US-201514866122-A
Country	US
Kind code	A1
Filing date	Sep 25, 2015
Priority date	Oct 17, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A host access instruction is received from one of a plurality of channels which are served in parallel. The host access instruction includes an address range of one or more addresses and a type of access. The address range and type of access are compared against a table of stored address ranges and stored types of access associated with any pending host access instructions. It is determined whether to execute the host access instruction based at least in part on the comparison. If it is decided to execute the host access instruction, the host access instruction is forwarded for execution and the address range and the type of access from the host access instruction are stored in the table.

First claim

What is claimed is:

1 . A system, comprising:
a blocking check engine configured to:
receive, from one of a plurality of channels which are served in parallel, a host access instruction which includes: (1) an address range of one or more addresses and (2) a type of access;
compare the address range and type of access against a table of: (1) stored address ranges of one or more addresses and (2) stored types of access associated with any pending host access instructions;
determine whether to execute the host access instruction based at least in part on the comparison; and
in the event it is determined to execute the host access instruction:
forward the host access instruction for execution; and
store the address range and the type of access from the host access is instruction in the table; and

the table.

2 . The system recited in claim 1 further comprising a blocking release interface configured to:
receive an indication that a pending host access instruction has completed; and
delete the stored address range and stored type of access associated with the pending host access instruction that has completed from the table.

3 . The system recited in claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

4 . The system recited in claim 1 , wherein the blocking check engine is configured to determine whether to execute the host access instruction, including by:
determining the type of access; in the event it is determined that the type of access is a read:
comparing the address range against all stored address ranges having a stored type of access of write;
determining if there is an overlap between (1) the address range and (2) all stored address ranges having a stored type of access of write;
in the event it is determined that there is an overlap between (1) and (2), deciding not to execute the host access instruction; and
in the event it is determined that there is no overlap between (1) and (2), deciding to execute the host access instruction; and
in the event it is determined that the type of access is a write:
comparing (3) the address range against (4) all stored address ranges, independent of stored type of access;
determining if there is an overlap between (3) and (4);
in the event it is determined that there is an overlap between (3) and (4), deciding not to execute the host access instruction; and
in the event it is determined that there is no overlap between (3) and (4), deciding to execute the host access instruction. cm 5 . The system recited in claim 3 , further comprising:
an embedded microprocessor; and a memory coupled to the embedded microprocessor, wherein the memory is configured to provide the embedded microprocessor with instructions which when executed cause the embedded microprocessor to:
generate a firmware access instruction which includes: (1) all addresses in a user range and (2) a third type of access other than read or write;
determine whether to unlock NAND storage; and
in the event it is determined to unlock the NAND storage, generate an indication that the firmware access instruction has completed.

6 . The system recited in claim 3 , further comprising:
an embedded microprocessor; and a memory coupled to the embedded microprocessor, wherein the memory is configured to provide the embedded microprocessor with instructions which when executed cause the embedded microprocessor to:
read and store one or more configuration settings associated with type of access blocking rules;
change the configuration settings so that a read type of access blocks any subsequent read type of access or subsequent write type of access;
generate a firmware access instruction which includes: (1) all addresses in a user range and a virtual range and (2) a read type of access;
determine whether to unlock NAND storage; and
in the event it is determined to unlock the NAND storage:
generate an indication that the firmware access instruction has completed; and
change the configuration settings to their stored values.

7 . A method, comprising:
receiving, from one of a plurality of channels which are served in parallel, a host access instruction which includes: (1) an address range of one or more addresses and (2) a type of access; comparing the address range and type of access against a table of: (1) stored address is ranges of one or more addresses and (2) stored types of access associated with any pending host access instructions; determining whether to execute the host access instruction based at least in part on the comparison; and in the event it is determined to execute the host access instruction:
forwarding the host access instruction for execution; and
storing the address range and the type of access from the host access instruction in the table.

8 . The method recited in claim 7 further comprising:
receiving an indication that a pending host access instruction has completed; and
deleting the stored address range and stored type of access associated with the pending host access instruction that has completed from the table.

9 . The method recited in claim 7 , wherein the method is performed by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

10 . The method recited in claim 7 , wherein determining whether to execute the host access instruction includes:
determining the type of access; in the event it is determined that the type of access is a read:
comparing the address range against all stored address ranges having a stored type of access of write;
determining if there is an overlap between (1) the address range and (2) all stored address ranges having a stored type of access of write;
in the event it is determined that there is an overlap between (1) and (2), deciding not to execute the host access instruction; and
in the event it is determined that there is no overlap between (1) and (2), deciding to execute the host access instruction; and
in the event it is determined that the type of access is a write:
comparing (3) the address range against (4) all stored address ranges, independent is of stored type of access;
determining if there is an overlap between (3) and (4);
in the event it is determined that there is an overlap between (3) and (4), deciding not to execute the host access instruction; and
in the event it is determined that there is no overlap between (3) and (4), deciding to execute the host access instruction.

11 . The method recited in claim 9 , further comprising using firmware that executes on an embedded microprocessor to:
generate a firmware access instruction which includes: (1) all addresses in a user range and (2) a third type of access other than read or write; determine whether to unlock NAND storage; and in the event it is determined to unlock the NAND storage, generate an indication that the firmware access instruction has completed.

12 . The method recited in claim 9 , further comprising using firmware that executes on an embedded microprocessor to:
read and store one or more configuration settings associated with type of access blocking rules; change the configuration settings so that a read type of access blocks any subsequent read type of access or subsequent write type of access; generate a firmware access instruction which includes: (1) all addresses in a user range and a virtual range and (2) a read type of access; determine whether to unlock NAND storage; and in the event it is determ

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Bao Shengkun
• Landin Kevin
• Nagarajan Ananthanarayanan
• Chan Kin Ming

Classifications

• G06F12/1441 Primary

  for a range · CPC title

• G06F12/1483

  using an access-table, e.g. matrix or list · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F13/126

  and has means for transferring I/O instructions and statuses between control unit and main processor · CPC title