Apparatus, system and method for protecting data

Patent metadata

Field	Value
Publication number	US-2016110241-A1
Application number	US-201514874773-A
Country	US
Kind code	A1
Filing date	Oct 5, 2015
Priority date	Oct 21, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

An apparatus and corresponding method for protecting stored data. The apparatus includes a first encoder, a memory, a second encoder and a comparator. The first encoder is configured to generate first redundancy bits using a protection method to protect input data bits, whereas the input data bits are assigned to at least one of a plurality of classes. The memory is configured to store selectively inverted input data bits and/or selectively inverted first redundancy bits, whereas the selective inversion is based on the assigned at least one of the plurality of classes. The second encoder is configured to generate second redundancy bits using the protection method by encoding the selectively inverted input data bits. The comparator is configured to generate an alarm signal if the second redundancy bits are different from the first redundancy bits.

First claim

1 . A method for protecting input data bits comprising:
assigning of input data bits to at least one of a plurality of classes, calculating first redundancy bits (R) based on the input data bits and the at least one of the plurality of classes, generating bits of a memory by storing and by selective inverting of input data bits and/or first redundancy bits, whereas the selective inverting is based on the at least one of the plurality of classes, calculating second redundancy bits (R′) based on a payload of the memory and generating an alarm signal if the second redundancy bits (R′) and the first redundancy bits (R) are different.

2 . The method according to claim 1 , wherein the memory is a register.

3 . The method according to claim 1 , wherein at least one bit of the input data bits is assigned to a first class of the plurality of classes and at least one other bit of the input data bits is assigned to a second class of the plurality of classes.

4 . The method according to claim 1 , wherein the plurality of classes represent different safety requirements.

5 . The method according to claim 1 , wherein the first redundancy bits (R) and the second redundancy bits (R′) are calculated by using one out of a group of the following protection methods: DMR, TMR, detectable ECC, correctable ECC or parity generation.

6 . The method according to claim 1 , wherein the first redundancy bits (R) and the second redundancy bits (R′) are calculated by each using a combination of at least two different protection methods out of a following group of protection methods: DMR, TMR detectable ECC, correctable ECC or parity generation.

7 . The method according to claim 1 , wherein the selective inverting is controlled by control signals.

8 . The method according to claim 1 , wherein the plurality of classes comprise combinatorial, unprotected, protected-fully-testable, protected-reduced-testable and non-testable classes.

9 . The method according to claim 8 , wherein for the protected-reduced-testable class only the payload is selectively inverted and whereas for the protected-fully-testable class all bits of memory are selectively inverted.

10 . The method according to claim 1 , wherein the order of input data bits is modified according to the assigned at least one of the plurality of classes before the first redundancy bits (R) are calculated.

11 . An apparatus for protecting data, comprising:
a first encoder configured to generate first redundancy bits (R) using a protection method to protect input data bits, whereas the input data bits are assigned to at least one of a plurality of classes, a memory configured to store selectively inverted input data bits and/or selectively inverted first redundancy bits, whereas the selective inversion is based on the assigned at least one of the plurality of classes, a second encoder configured to generate second redundancy bits (R′) using the protection method by encoding the selectively inverted input data bits and a comparator configured to generate an alarm signal if the second redundancy bits (R′) are different from the first redundancy bits (R).

12 . The apparatus of claim 11 , wherein the protection method is one of the following: Double Modular Redundancy (DMR), Triple Modular Redundancy (TMR), detectable Error Correction Codes (ECC), correctable ECC or parity generation.

13 . The apparatus according to claim 11 , wherein the encoder comprises a sort module configured to reorder the input data bits assigned to at least one of the plurality of classes.

14 . The apparatus according to claim 11 , wherein the encoder comprises an inverter configured to selectively invert the input data bits assigned to at least one of the plurality of classes.

15 . A system comprising an apparatus according to claim 11 , and a device, wherein the device is configured to provide at least one of a plurality of control signals to the apparatus and to receive an alarm signal.

16 . The system according to claim 15 , wherein at least one of a plurality of control signals defines self-test phases which determine the selective inversion of input data bits and/or the selective inversion of first redundancy bits (R′).

17 . A system comprising a plurality of apparatus according to claim 11 , and a device, wherein the device is configured to receive a reduced alarm signal and the reduced alarm signal is configured to indicate correctable errors and uncorrectable errors.

Assignees

• Infineon Technologies Ag

Inventors

• Busch Holger

Classifications

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title