Branch prediction suppression

Patent metadata

Field	Value
Publication number	US-2016110202-A1
Application number	US-201414519697-A
Country	US
Kind code	A1
Filing date	Oct 21, 2014
Priority date	Oct 21, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A data processing apparatus 2 contains branch prediction circuitry 10 including a micro branch target buffer 28, a full branch target buffer 30 and a global history buffer 32. The branch target buffer entries 40 contain history data 42, 44 which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data 42, 44 indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry 28, 30, 32 is suppressed for these following blocks of program instructions so as to save energy.

First claim

We claim:

1 . Apparatus comprising:
one or more branch prediction circuits to predict whether a given block of program instructions contains a branch instruction; and prediction suppression circuitry to use history data representing previous branch behaviour of a following block of program instructions sequentially following said given block of program instructions to suppress at least one of said one or more branch prediction circuits predicting whether said following block of program instructions contains a branch instruction.

2 . Apparatus as claimed in claim 1 , wherein said history data represents previous branch behaviour of a plurality of following blocks of program instructions sequentially following said given block and said prediction suppression circuitry uses history data to suppress at least one of said one or more branch prediction circuits predicting if one or more of said plurality of following blocks of program instructions contain a branch.

3 . Apparatus as claimed in claim 2 , wherein said plurality of following blocks of program instructions comprises two following blocks of program instructions.

4 . Apparatus as claimed in claim 1 , wherein said history data comprises a count of following blocks of program instructions predicted not to contain a branch.

5 . Apparatus as claimed in claim 1 , wherein said one or more branch prediction circuits comprise at least one branch target buffer to store branch target data specifying addresses of blocks of program instructions predicted to contain a branch.

6 . Apparatus as claimed in claim 5 , wherein said history data is part of said branch target data.

7 . Apparatus as claimed in claim 5 , wherein said at least one branch target buffer comprises a micro branch target buffer and a full branch target buffer, said micro branch target buffer to predict whether said given block of program instructions contains a branch more quickly than said full branch target buffer, and said full branch target buffer to store branch target data in respect of more blocks of program instructions than said micro branch target buffer.

8 . Apparatus as claimed in claim 7 , wherein said prediction suppression circuitry is controlled by said micro branch target buffer and uses said history data to suppress said full branch target buffer predicting if said following block of program instructions contains a branch.

9 . Apparatus as claimed in claim 7 , wherein both said micro branch target buffer and said full branch target buffer store at least some of said history data.

10 . Apparatus as claimed in claim 5 , wherein said at least one branch target buffer uses said history data to control said prediction suppression circuitry to suppress said at least one branch target buffer itself predicting if said following block of program instructions contains a branch.

11 . Apparatus as claimed in claim 7 , wherein said one or more branch prediction circuits include a global history buffer to predict taken and not taken behaviour of branch instructions and said prediction suppression circuitry uses said history data to suppress said global history buffer predicting if said following block of program instructions contains a branch.

12 . Apparatus as claimed in claim 1 , wherein said given block of program instructions and said following block of program instructions each contain a plurality of program instructions.

13 . Apparatus as claimed in claim 1 , wherein said given block of program instructions is a branch-containing block of program instructions predicted by said one or more prediction circuits to contain a branch.

14 . Apparatus as claimed in claim 13 , comprising history data generating circuitry to monitor if a block of program instructions following said branch-containing block of program instructions contains a branch and to generate said history data indicating if said block of program instructions following said branch-containing block of program instructions contains a branch.

15 . Apparatus comprising:
one or more branch prediction means for predicting whether a given block of program instructions contains a branch instruction; and prediction suppression means for using history data representing previous branch behaviour of a following block of program instructions sequentially following said given block of program instructions to suppress at least one of said one or more branch prediction means predicting whether said following block of program instructions contains a branch instruction.

16 . A method comprising the steps of:
predicting with one or more branch prediction circuits whether a given block of program instructions contains a branch instruction, wherein using history data representing previous branch behaviour of a following block of program instructions sequentially following said given block of program instructions to suppress at least one of said one or more branch prediction means predicting whether said following block of program instructions contains a branch instruction.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Filippo Michael Alan
• Elwood Matthew Paul
• Farooq Umar
• George Adam

Classifications

• G06F9/3844 Primary

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/3806

  using address prediction, e.g. return stack, branch history buffer · CPC title

• G06F9/3848

  using hybrid branch prediction, e.g. selection between prediction techniques · CPC title

• G06F9/3808

  for instruction reuse, e.g. trace cache, branch target cache · CPC title