Display driver circuit including high power/low power interfaces and display system

Patent metadata

Field	Value
Publication number	US-2016109934-A1
Application number	US-201514919223-A
Country	US
Kind code	A1
Filing date	Oct 21, 2015
Priority date	Oct 21, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A display driver circuit can include an input selector circuit configured to receive first display data from a high power processor circuit and configured to operate in a normal mode in which the first display data is provided and in a dormant mode in which no image data is provided to the input selector circuit and configured to receive second display data from a low power processor circuit that is configured provide the second display data when the high power processor circuit is in the dormant mode. A controller circuit, can be coupled to switch the first display data or the second display data through the input selector circuit based on the mode of operation of the high power processor circuit.

First claim

What is claimed is:

1 . A display system comprising:
a first processor circuit configured to generate first data and output the first data; a second processor circuit configured to generate second data and output the second data; and a display driver circuit configured to generate a driver signal based on one of the first data received from the first processor circuit and the second data received from the second processor circuit.

2 . The display system of claim 1 , further comprising:
a display panel coupled to the display driver circuit, wherein the first data and the second data comprise display data corresponding to an image displayed on the display panel.

3 . The display system of claim 1 , wherein the first processor circuit transmits the first data to the display driver circuit through a first interface,
the second processor circuit transmits the second data to the display driver circuit through a second interface, and a transmission rate of the first interface is higher than a transmission rate of the second interface.

4 . The display system of claim 1 , wherein the first processor circuit comprises an application processor circuit configured to control an operation of an electronic device on which the display system is mounted, and
the second processor circuit comprises a micro-control unit (MCU) configured to control a communication module or a sensor module included in the electronic device.

5 . The display system of claim 1 , wherein the second processor circuit generates the second data based on an external sensing signal when the first processor circuit is in a dormant state.

6 . The display system of claim 1 , wherein the first processor circuit transmits a command signal indicating a lower-power operating mode to the second processor circuit and enters a dormant state, and the second processor circuit generates the second data in response to the command signal.

7 . The display system of claim 6 , wherein the second processor circuit generates the second data in response to a sensing signal when an external sensing signal is of a first type, and transmits the sensing signal and a normal operation request signal when the sensing signal is of a second type.

8 . The display system of claim 1 , wherein the second processor circuit transmits a trigger signal indicating transmission of the second data along with the second data to the display driver circuit.

9 . The display system of claim 1 , further comprising a third processor circuit configured to generate third data and output the third data,
wherein the display driver circuit generates a driver signal based on the first data received from the first processor circuit, the second data received from the second processor circuit, or the third data received from the third processor circuit.

10 . A mobile electronic device comprising the display system of claim 1 .

11 . A display driver circuit comprising:
an input selector configured to select one of first data received through a first interface and second data received through a second interface, as input data, in response to a data selection signal; an input control unit configured to generate the data selection signal according to an operating mode; and a timing controller configured to perform a processing operation to display an image including the input data on a display panel.

12 . The display driver circuit of claim 11 , wherein the first data and the second data are received from a first high-power processor circuit and a second low-power processor circuit, respectively.

13 . The display driver circuit of claim 11 , further comprising a storage unit configured to store the input data,
wherein the storage unit comprises a plurality of storage regions configured to sequentially store a plurality of pieces of input data that are output by the input selector in a temporal sequence.

14 . The display driver circuit of claim 13 , further comprising:
an output selector configured to select one of the plurality of pieces of data output by the plurality of storage regions, as output data, in response to an output selection signal; and an output control unit configured to generate the output selection signal based on the operating mode or a time period.

15 . The display driver circuit of claim 14 , wherein the output control unit comprises a clock counter configured to count applied clocks, determine the time period, and generate the output selection signal for sequentially selecting data for each time period.

16 . A display driver circuit comprising:
an input selector circuit configured to receive first display data from a high power processor circuit configured to operate in a normal mode in which the first display data is provided and in a dormant mode in which no image data is provided to the input selector circuit and configured to receive second display data from a low power processor circuit that is configured provide the second display data when the high power processor circuit is in the dormant mode; and a controller circuit, coupled to switch the first display data or the second display data through the input selector circuit based on the mode of operation of the high power processor circuit.

17 . The circuit of claim 16 wherein the controller circuit is coupled to the first display data, wherein the controller circuit is configured to determine that the mode of operation of the high power processor circuit is normal based on a content of the first display.

18 . The circuit of claim 16 further comprising:
a memory coupled to an output of the input selector circuit, wherein the controller circuit is configured to store the output of the input selector circuit in the memory when the high power processor circuit is in the dormant mode and is configured to bypass the memory when the high power processor circuit is in the normal mode.

19 . The circuit of claim 16 further comprising;
a memory coupled to an output of the input selector circuit, wherein the memory further comprises:
a first memory region configured to store the first display data provided via the output of the input selector circuit; and
a second memory region configured to store the second display data provided via the output of the input selector circuit.

20 . The circuit of claim 16 wherein the second display data comprises only a portion of a frame of image data that is updated within a static image display responsive to an indication by the low power processor circuit.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Soo-Young
• Kim Yang-Hyo
• Kim Sun-Young
• Kim Chul-Ho
• Kim Do-Kyung
• Yun Jung-Hee

Classifications

• G06F1/3265

  Power saving in display device · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G09G2310/0243

  Details of the generation of driving signals · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title