Novel low cost, low power high performance smp/asmp multiple-processor system

Patent metadata

Field	Value
Publication number	US-2016109922-A1
Application number	US-201414580044-A
Country	US
Kind code	A1
Filing date	Dec 22, 2014
Priority date	Oct 16, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A processing system includes multiple processors in which first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). A third processor may be included that also operates at the first clock frequency and the first supply voltage at all times. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. A controller enables control and fast-switching between the two modes for the switchable processor. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.

First claim

What is claimed is:

1 . A multi-processor (MP) processing system, comprising:
a plurality of processors comprising,
a first processor configured to receive and operate in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined operating voltage, and
a second processor configured to receive and operate in accordance with either the first clock signal or a second clock signal having a second predetermined frequency different from the first predetermined frequency and receive and operate in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage;
a controller coupled to at least the second processor and configured to switch operation of the second processor between a first mode of operation and a second mode of operation, wherein:
when in the first mode of operation, the second processor receives and operates in accordance with the first clock signal and the first supply voltage, and
when in the second mode of operation, the second processor receives and operates in accordance with the second clock signal and the second supply voltage; and
wherein the first processor is further configured to only receive and operate in accordance with the first clock signal and the first supply voltage during both the first mode and second mode of operation.

2 . The MP processing system in accordance with claim 1 wherein the plurality of processors further comprise:
a third processor configured to only receive and operate in accordance with the first clock signal and the first supply voltage during both the first mode and second mode of operations.

3 . The MP processing system in accordance with claim 2 wherein the plurality of processors further comprise:
a fourth processor configured to only receive and operate in accordance with the first clock signal and the first supply voltage during both the first mode and second mode of operations.

4 . The MP processing system in accordance with claim 3 wherein the plurality of processors further comprise:
a fifth processor, a sixth processor, a seventh processor and an eighth processor each configured to only receive and operate in accordance with the first clock signal and the first supply voltage during both the first mode and second mode of operations.

5 . The MP system in accordance with claim 1 , further comprising:
a clock generation circuit coupled to the controller and configured to generate and output the first clock signal and the second clock signal, the first clock signal input to the first processor; an operating voltage generation circuit coupled to the controller and configured to generate and output the first supply voltage to the first processor and output the second supply voltage to the second processor; a switching circuit disposed between the clock generation circuit and the second processor and configured to receive the first clock signal and the second clock signal and output the first clock signal or the second clock signal to the second processor, wherein during the first mode of operation the first clock signal is output to the second processor and during the second mode of operation the second clock signal is output to the second processor; and wherein during the first and second modes of operation the first clock signal is output to the first processor.

6 . The MP processing system in accordance with claim 1 , further comprising:
a voltage regulator circuit coupled to the controller and configured to:
generate and output the second supply voltage to the second processor when in the second mode of operation, and
output the first supply voltage to the second processor when in the second mode of operation.

7 . The MP processing system in accordance with claim 1 , further comprising:
a clock generation and switching circuit coupled to the controller and configured to generate the first clock signal and the second clock signal and glitchlessly switch between the first clock signal or the second clock signal for output to the second processor.

8 . The system in accordance with claim 1 , further comprising:
cache memory coupled to the first and second processors; and a clock-domain crossing (CDC) and bypass circuit responsive to the controller and coupled to the second processor and the cache memory, and further configured to provide a clock-domain crossing function between the second processor and the cache memory during the second mode of operation and provide a bypassing function during the first mode of operation.

9 . The MP processing system in accordance with claim 1 wherein the controller is further configured to dynamically switch operation of the second processor between the first mode of operation and the second mode of operation in response to a mode selection signal.

10 . The MP processing system in accordance with claim 9 wherein the mode selection signal is generated at least in part based on an activation or deactivation of a processor within the plurality of processors.

11 . The MP processing system in accordance with claim 9 , wherein the mode selection signal is generated in response to at least a one of the following: load information, use information, cache miss rate, memory bandwidth information or power consumption information.

12 . The MP processing system in accordance with claim 1 wherein the controller comprises at least one of a finite state machine (FSM), a processor, a microcontroller or logic circuitry.

13 . The MP processing system in accordance with claim 1 wherein the MP processing system is disposed on a single semiconductor substrate.

14 . An apparatus, comprising:
a plurality of processors configured to perform multiprocessing functions, the plurality of processors comprising a plurality of first processors and a second processor; a controller configured to control operation of the second processor in a first mode and a second mode; a clock generation circuit coupled to the controller and configured to generate and output a first clock signal and a second clock signal; a switching circuit disposed between the clock generation circuit and the second processor and configured to receive the first and second clock signals and select one for output to the second processor, wherein during the first mode of operation the first clock signal is output to the second processor and during the second mode of operation the second clock signal is output to the second processor; wherein during the first mode of operation and the second mode of operation the first clock signal is input to each of the plurality of first processors; cache memory coupled to and configured for use with the plurality of processors; and a clock-domain crossing (CDC) and bypass circuit responsive to the controller and coupled to the second processor and the cache memory, and further configured to provide a clock-domain crossing function between the second processor and the cache memory during the second mode of operation and provide a bypassing function during the first mode of operation.

15 . The apparatus in accordance with claim 14 wherein the plurality of first processors further comprises a fourth processor.

16 . The apparatus in accordance with claim 15 wherein the plurality of first processors further comprises: a fifth processor, a sixth processor, a seventh processor and an eighth processor.

17 . The apparatus in accordance with claim 14 , further comprising:
an operating voltage generatio

Assignees

• Futurewei Technologies Inc

Inventors

• Chen Wei
• Wei Konggang
• Yang Tongzeng

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title