Direct printed circuit routing to stacked opto-electrical ic packages

Patent metadata

Field	Value
Publication number	US-2016109668-A1
Application number	US-201414517477-A
Country	US
Kind code	A1
Filing date	Oct 17, 2014
Priority date	Oct 17, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

An optical transmitter may include a chip stack that includes an electrical IC that is mounted using solder balls to a photonic chip. These solder connections permit the electrical IC and the photonic chip to communicate. In addition, the transmitter may include a PCB coupled to the stack so that electrical signals in the PCB are transmitted to the IC and photonic chip (and vice versa). Instead of coupling the PCB to the stack using wire bonds attached to pads on a surface of the photonic chip, at least a portion of the PCB is disposed between the photonic chip and electrical IC. The PCB may also include bond pads used to form a direct solder connection to the electrical IC. As such, the electrical IC may include direct solder connections to both the PCB and the photonic chip.

First claim

We claim:

1 . A photonic chip, comprising:
a first surface and a second surface that are both normal to a common direction, wherein the second surface is recessed relative to the first surface along the common direction to form an alignment area, wherein a depth of the alignment area is greater than or equal to a thickness of a portion of a printed circuit board (PCB), thereby permitting a top surface of the PCB to substantially align with the first surface when placed in the alignment area; a bonding region disposed on the first surface, the bonding region comprises a plurality of bond pads configured to form electrical connections to an electrical integrated circuit (IC); and an optical component electrically coupled to at least one of the plurality of bond pads, the optical component is configured to transmit an optical signal within the photonic chip.

2 . The photonic chip of claim 1 , further comprising:
a raised feature extending from the second surface along the common direction, wherein a bonding surface of the raised feature is substantially within a same plane as the first surface, the bonding surface is configured to couple to the electrical IC.

3 . The photonic chip of claim 2 , wherein the bonding surface of the raised feature includes a plurality of bond pads configured to form solder connections to the electrical IC.

4 . The photonic chip of claim 3 , wherein the plurality of bond pads are electrically isolated such that electrical signals are not received or transmitted to the electrical IC via the plurality of bond pads.

5 . The photonic chip of claim 2 , wherein the raised feature includes a waveguide for routing the optical signal, wherein the optical signal is received from an external light source at a first side of the photonic chip and emitted, via the waveguide, on a second, opposite side of the photonic chip.

6 . The photonic chip of claim 1 , wherein the optical component comprises a modulator configured to alter a phase of the optical signal based on signals received via the at least one of the plurality of bond pads.

7 . An optical system, comprising:
an electrical IC comprising a bottom surface; a photonic chip comprising a top surface and a recessed surface both facing the bottom surface of the IC, wherein the recessed surface is further from the bottom surface of the IC than the top surface relative to a direction that is normal to the top and recessed surfaces, and wherein the IC overlays both the top and recessed surfaces; and a portion of a signal routing material disposed between the bottom surface of the IC and the recessed surface of the photonic chip, the portion of the signal routing material and the top surface of the photonic chip each comprising a plurality of respective electrical connections to the bottom surface of the IC.

8 . The optical system of claim 7 , wherein a top surface of the portion of the signal routing material comprising the plurality of electrical connections is within a same plane as the top surface of the photonic chip, and wherein the signal routing material comprises one of a rigid PCB and a flexible PCB.

9 . The optical system of claim 7 , wherein the electrical IC comprises at least one redistribution layers establishing a signal path to transfer electrical signals between the portion of the signal routing material and the photonic chip, wherein there is no direct electrical connection between the portion of the signal routing material and the photonic chip.

10 . The optical system of claim 7 , wherein a gap between the recessed surface of the photonic chip and the portion of the signal routing material is filled with an underfill material.

11 . The optical system of claim 7 , wherein the photonic chip further comprises:
a raised feature extending from the recessed surface towards the bottom surface of the IC, wherein a bonding surface of the raised feature is within a same plane as the top surface of the photonic chip, the bonding surface is coupled to the bottom surface of the IC, wherein the portion of the signal routing material includes one or more surface defining an aperture through which the raised feature extends.

12 . The optical system of claim 11 , wherein the bonding surface of the raised feature includes a plurality of solder connections to the bottom surface of the IC.

13 . The optical system of claim 11 , wherein the raised feature includes an optical component for routing an optical signal received from an external light source at a first side of the photonic chip to a second, opposite side of the photonic chip.

14 . The optical system of claim 7 , further comprising:
a light source configured to transmit an optical signal into the photonic chip where the optical signal is modified; and a connector configured to receive the modified optical signal from the photonic chip and transmit the modified optical signal onto an optical cable.

15 . A method, comprising:
connecting a signal routing material to a bottom surface of an electrical IC using a first plurality of electrical connections; disposing a portion of the signal routing material comprising the first plurality of electrical connections in an alignment region of a photonic chip, the alignment region is defined, at least in part, by a distance between a recessed surface of the photonic chip and a top surface of the photonic chip relative to a direction normal to both the recessed and top surfaces, wherein the top and recessed surfaces both face the bottom surface of the IC, and wherein the portion of the signal routing material is between the bottom surface of the IC and the recessed surface of the photonic chip; and connecting the bottom surface of the IC to the top surface of the photonic chip using a second plurality of electrical connections.

16 . The method of claim 15 , wherein disposing the portion of the signal routing material in the alignment region is performed after connecting the signal routing material to the bottom surface of an electrical IC, wherein the first plurality of electrical connections comprise solder connections.

17 . The method of claim 15 , wherein connecting the bottom surface of the IC to the top surface of the photonic chip is performed after disposing the portion of the signal routing material in the alignment region, wherein the second plurality of electrical connections comprise solder connections.

18 . The method of claim 15 , further comprising:
filling a gap between the recessed surface of the photonic chip and the portion of the signal routing material using an underfill material.

19 . The method of claim 15 , wherein a top surface of the portion of the signal routing material comprising the first plurality of electrical connections is within a same plane as the top surface of the photonic chip.

20 . The method of claim 15 , wherein the photonic chip further comprises:
a raised feature extending from the recessed surface towards the bottom surface of the IC, wherein a bonding surface of the raised feature is within a same plane as the top surface of the photonic chip, the bonding surface is coupled to the bottom surface of the IC, wherein the portion of the PCB includes one or more surface defining an aperture through which the raised feature extends.

Assignees

• Cisco Tech Inc

Inventors

• Pfnuer Stefan Martin
• Traverso Matthew Joseph
• Dama Bipin

Classifications

• G02B6/428 Primary

  containing printed circuit boards [PCB] · CPC title

• G02B6/4232

  using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072) · CPC title

• G02F1/011

  in optical waveguides, not otherwise provided for in this subclass · CPC title

• G02B6/4257 Primary

  having a supporting carrier or a mounting substrate or a mounting plate (G02B6/3648 takes precedence) · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title