Display substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016104803-A1
Application number	US-201514702479-A
Country	US
Kind code	A1
Filing date	May 1, 2015
Priority date	Oct 14, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A display substrate includes a base substrate, a gate pattern, an active pattern and a data metal pattern. The gate pattern includes a gate electrode on the base substrate. The active pattern overlaps the gate electrode and includes a first active layer, a second active layer and a third active layer. The first active layer includes first amorphous silicon (a-Si:H). The second active layer is disposed on the first active layer and includes second amorphous silicon of which a concentration of hydrogen is higher than that of the first amorphous silicon. The third active layer is disposed on the second active layer and includes third amorphous silicon of which a concentration of hydrogen is substantially the same as that of the first amorphous silicon. The data metal pattern is disposed on the active pattern and includes source and drain electrodes spaced apart from each other.

First claim

What is claimed is:

1 . A display substrate comprising:
a base substrate; a gate pattern comprising a gate electrode on the base substrate; an active pattern overlapping the gate electrode, the active pattern comprising:
a first active layer comprising first amorphous silicon (a-Si:H);
a second active layer on the first active layer, the second active layer including second amorphous silicon of which a concentration of hydrogen is higher than that of the first amorphous silicon; and
a third active layer on the second active layer, the third active layer including third amorphous silicon of which a concentration of hydrogen is substantially lower than that of the second active layer ; and
a data metal pattern on the active pattern, the data metal pattern comprising source and drain electrodes spaced apart from each other.

2 . The display substrate of claim 1 , wherein the third active layer is substantially the same as the first active layer.

3 . The display substrate of claim 1 , wherein the first amorphous silicon in the first active layer includes Si—H bond.

4 . The display substrate of claim 3 , wherein the second amorphous silicon in the second active layer includes the Si—H bond and Si—H 2 bond.

5 . The display substrate of claim 4 , wherein an amount of the Si—H 2 bond in the second active layer is about 5 mol % to about 10 mol % of a total mol % of the Si—H bond and the Si—H 2 bond.

6 . The display substrate of claim 1 , wherein the first active layer has a thickness of about 100 Å to about 150 Å.

7 . The display substrate of claim 1 , wherein the second active layer has a thickness of about 1000 Å to about 1500 Å.

8 . The display substrate of claim 1 , wherein the third active layer has a thickness of about 300 Å to about 500 Å.

9 . The display substrate of claim 1 , further comprising:
an ohmic contact layer on the third active layer and comprising impurity-doped silicon.

10 . The display substrate of claim 9 , wherein the impurity-doped silicon includes phosphorous.

11 . A method of manufacturing a display substrate, the method comprising:
forming a gate pattern on a base substrate, the gate pattern comprising a gate electrode; forming an active layer by sequentially depositing a first active layer, a second active layer and a third active layer on the base substrate on which the gate pattern is formed, wherein the first active layer includes first amorphous silicon (a-Si:H), the second active layer includes second amorphous silicon of which a concentration of hydrogen is higher than that of the first amorphous silicon, and the third active layer includes third amorphous silicon of which a concentration of hydrogen is substantially lower than that of the second active layer; and forming an active pattern by patterning the active layer.

12 . The method of claim 11 , wherein the third active layer is substantially the same as the first active layer.

13 . The method of claim 11 , wherein the first active layer and the third active layer are formed by a deposition process using a mixed gas including silane (Si) and hydrogen (H 2 ), and
a volume ratio of silane and hydrogen in the mixed gas is about 1:4 to about 1:5.

14 . The method of claim 13 , wherein the first active layer has a thickness of about 100 Å to about 150 Å, and the third active layer has a thickness of about 300 Å to about 500 Å.

15 . The method of claim 14 , wherein the first active layer and the third active layer have a deposition rate of about 5 Å/sec to about 6 Å/sec.

16 . The method of claim 11 , wherein the second active layer is formed by a deposition process using a mixed gas including silane (Si) and hydrogen (H 2 ), and
a volume ratio of silane and hydrogen in the mixed gas is about 1:6 to about 1:7.

17 . The method of claim 16 , wherein the second amorphous silicon in the second active layer includes Si—H bond and Si—H 2 bond, and an amount of the Si—H 2 bond in the second active layer is about 5 mol % to about 10 mol % of a total mol % of the Si—H bond and the Si—H 2 bond.

18 . The method of claim 16 , wherein the second active layer has a thickness of about 1000 Å to about 1500 Å.

19 . The method of claim 16 , wherein the second active layer has a deposition rate of about 20 Å/sec to about 30 Å/sec.

20 . The method of claim 11 , further comprising:
forming an ohmic contact layer comprising impurity-doped silicon on the third active layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Ahn Tae-Young
• Oh Ji-Hoon

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6732

  Bottom-gate only TFTs · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title