Displays with Intra-Frame Pause
US-2015269897-A1 · Sep 24, 2015 · US
US2016104757A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016104757-A1 |
| Application number | US-201514700355-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 30, 2015 |
| Priority date | Oct 13, 2014 |
| Publication date | Apr 14, 2016 |
| Grant date | — |
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Provided is an organic light emitting diode display device, including a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, in which the etching prevention member overlaps with the fanout line and the peripheral potential voltage line.
Opening claim text (preview).
What is claimed is: 1 . An organic light emitting diode display device, comprising: a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, wherein the etching prevention member overlaps with the fanout line and the peripheral potential voltage line. 2 . The organic light emitting diode display device as claimed in claim 1 , further comprising a sealing groove is on the third insulating layer of the peripheral unit and overlapping the etching prevention member and the fanout line. 3 . The organic light emitting diode display device as claimed in claim 1 , wherein the third insulating layer includes a third inorganic insulating layer contacting the second insulating layer and a third organic insulating layer covering the third inorganic insulating layer. 4 . The organic light emitting diode display device as claimed in claim 3 , further comprising a contact hole in the third insulating layer of the pixel unit and including an inorganic contact hole of the third inorganic insulating layer and an organic contact hole of the third organic insulating layer, the inorganic contact hole and the organic contact hole having a same boundary line and contacting each other. 5 . The organic light emitting diode display device as claimed in claim 1 , further comprising: a semiconductor on the pixel substrate of the pixel unit; a first gate metal line on a same layer as the fanout line of the pixel unit; a second gate metal line on a same layer as the etching prevention member of the pixel unit; and a data metal line on a same layer as the peripheral potential voltage line of the pixel unit. 6 . The organic light emitting diode display device as claimed in claim 5 , wherein: the first gate metal line includes a scan line transferring a scan signal, and the data metal line includes a data line and a driving voltage line transferring a data signal and a driving voltage, respectively. 7 . The organic light emitting diode display device as claimed in claim 6 , wherein: the semiconductor includes a switching channel of a switching transistor connected with the scan line and the data line and a driving channel of a driving transistor connected with the switching transistor, and the driving channel is curved in a plan view. 8 . The organic light emitting diode display device as claimed in claim 7 , further comprising: a storage capacitor including a first storage electrode on the first insulating layer and overlapping the driving channel; and a second storage electrode on the second insulating layer, the second insulating layer covering the first storage electrode and overlapping the first storage electrode, wherein: the first storage electrode is a driving gate electrode of the driving transistor, and the second gate metal line includes the second storage electrode. 9 . The organic light emitting diode display device as claimed in claim 6 , wherein the fanout line is connected with the data line and transfers the data signal to the data line from the outside. 10 . The organic light emitting diode display device as claimed in claim 6 , wherein: the organic light emitting diode includes a pixel electrode on the passivation layer, an organic emission layer on the pixel electrode, and a common electrode on the organic emission layer, and the peripheral potential voltage line is a peripheral common voltage line transferring a common voltage to the common electrode or a peripheral driving voltage line transferring the driving voltage to the pixel electrode. 11 . A manufacturing method of an organic light emitting diode display device, the manufacturing method comprising: forming a first insulating layer on a pixel substrate including a pixel unit and a peripheral unit; forming a fanout line on the first insulating layer of the peripheral unit; forming a second insulating layer on the first insulating layer and the fanout line; forming an etching prevention member on the second insulating layer of the peripheral unit; forming a third insulating layer on the second insulating layer and the etching prevention member; forming a peripheral potential voltage line transferring a potential voltage on the third insulating layer of the peripheral unit; forming a passivation layer on the third insulating layer; and forming an organic light emitting diode on the passivation layer of the pixel unit, wherein the etching prevention member overlaps with the fanout line and the peripheral potential voltage line. 12 . The manufacturing method as claimed in claim 11 , further comprising: forming a sealing groove on the third insulating layer of the peripheral unit, wherein the sealing groove overlaps the etching prevention member and the fanout line. 13 . The manufacturing method as claimed in claim 12 , wherein: the third insulating layer includes a third inorganic insulating layer contacting the second insulating layer and a third organic insulating layer covering the third inorganic insulating layer, and forming of the sealing groove includes forming a contact hole in the third insulating layer by integrally etching the third inorganic insulating layer and the third organic insulating layer.
integrated with passive devices, e.g. auxiliary capacitors · CPC title
Interconnections, e.g. scanning lines · CPC title
comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title
having a particular composition, shape or crystalline structure of the active layer · CPC title
wherein the TFTs are in active matrices · CPC title
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