Package structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016104652-A1
Application number	US-201514684574-A
Country	US
Kind code	A1
Filing date	Apr 13, 2015
Priority date	Oct 9, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A method for fabricating a package structure is provided, which includes the steps of: forming a wiring layer on a carrier by electroplating; disposing at least one electronic component on the wiring layer; forming on the carrier an insulating layer that encapsulates the wiring layer and the electronic component; and removing the carrier. With the single wiring layer having one surface electrically connected the at least one electronic component and the other surface electrically connected to a plurality of conductive elements, the package structure has a signal transmission path that is shortened.

First claim

What is claimed is:

1 . A package structure, comprising:
an insulating layer having a first surface and a second surface opposite to the first surface; a wiring layer formed in the insulating layer by electroplating and having a surface exposed from the first surface of the insulating layer; and at least one electronic component embedded in the insulating layer and electrically connected to the wiring layer.

2 . The package structure of claim 1 , wherein the wiring layer is embedded in the first surface of the insulating layer.

3 . The package structure of claim 1 , wherein the surface of the wiring layer exposed from the first surface of the insulating layer is flush with or lower than the first surface of the insulating layer.

4 . The package structure of claim 1 , wherein the wiring layer comprises a plurality of conductive traces, and a plurality of conductive pads bonded and electrically connected to the electronic component.

5 . The package structure of claim 1 , wherein the electronic component is an active element, a passive element, or a combination thereof.

6 . The package structure of claim 1 , further comprising a plurality of conductive elements formed on the first surface of the insulating layer and electrically connected to the wiring layer.

7 . The package structure of claim 1 , wherein the insulating layer is made of a molding compound, a primer or a dielectric material.

8 . The package structure of claim 1 , further comprising another electronic component that is independent from and electrically isolated from the at least one electronic component.

9 . A method of fabricating a package structure, comprising the steps of:
forming a wiring layer on a carrier by electroplating; disposing at least one electronic component on the wiring layer, and electrically connecting the electronic component to the wiring layer; forming on the carrier an insulating layer that encapsulates the wiring layer and the electronic component and a first surface bonded to the carrier and a second surface opposite to the first surface; and removing the carrier to expose the wiring layer and the first surface of the insulating layer.

10 . The method of claim 9 , wherein the wiring layer has a surface flush with or lower than the first surface of the insulating layer.

11 . The method of claim 9 , wherein the wiring layer comprises a plurality of conductive traces, and a plurality of conductive pads bonded and electrically connected to the electronic component.

12 . The method of claim 9 , wherein the electronic component is an active element, a passive element, or a combination thereof.

13 . The method of claim 9 , further comprising forming a plurality of conductive elements on the first surface of the insulating layer, and electrically connecting the conductive elements to the wiring layer.

14 . The method of claim 9 , wherein the insulating layer is made of a molding compound, a primer or a dielectric material.

15 . The method of claim 9 , further comprising disposing on the wiring layer another electronic component that is independent from and electrically isolated from the at least one electronic component.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping
• Liu Chih-Wen
• Wu Tang-I
• Hu Shu-Wei

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07507

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title

• H10W72/072

  of bump connectors · CPC title