Method of use time management for semiconductor device and semiconductor device including use time managing circuit

Patent metadata

Field	Value
Publication number	US-2016104522-A1
Application number	US-201514874568-A
Country	US
Kind code	A1
Filing date	Oct 5, 2015
Priority date	Oct 13, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

First claim

What is claimed is:

1 . A use time managing method of a semiconductor device, the method comprising:
(1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

2 . The use time managing method as set forth in claim 1 , further comprising:
generating adjusting information when the detected use time reaches a reference time value; and adjusting an operation for an internal circuit of the semiconductor device based on the adjusting information.

3 . The use time managing method as set forth in claim 2 , wherein adjusting the operation of the internal circuit includes changing an output voltage level of a voltage generator of the semiconductor device.

4 . The use time managing method as set forth in claim 2 , wherein adjusting the operation of the internal circuit includes changing an amount of delay time of internal signals of the semiconductor device.

5 . The use time managing method as set forth in claim 2 , wherein adjusting the operation of the internal circuit includes changing a driving capability of drivers of the semiconductor device.

6 . The use time managing method as set forth in claim 2 , wherein adjusting the operation of the internal circuit includes changing a sensing capability of a sense amplifier of the semiconductor device.

7 . The use time managing method as set forth in claim 2 , wherein the semiconductor device is a dynamic random access memory including a plurality of memory cells each including a single access transistor and a single storage capacitor.

8 . The use time managing method as set forth in claim 1 , wherein each of the plurality of unit storage activation signals is generated by counting a number of refresh commands.

9 . The use time managing method as set forth in claim 1 , wherein each of the plurality of unit storage activation signals is generated by dividing a clock signal, the clock signal being generated by a clock generator of the semiconductor device.

10 . The use time managing method as set forth in claim 1 , wherein the cumulatively storing data is performed by programming, for each occurrence the generated unit storage activation signals, one of an antifuse, e-fuse or a flash memory cell.

11 . A use time managing method of a semiconductor device, comprising:
monitoring accumulated operation time of the semiconductor device by nonvolatilely updating cumulative use time of the semiconductor device in units of preset time periods during an operation of the semiconductor device; reading the cumulative use time of the semiconductor device to check whether the cumulative use time has reached a reference time value; generating adjusting information when the cumulative use time reaches the reference time value; and adjusting an operation of an internal circuit of the semiconductor device based on the adjusting information.

12 . The use time managing method as set forth in claim 11 , wherein the cumulative use time is obtained by dividing a clock signal, the clock signal being generated by a clock generator of the semiconductor device.

13 . The use time managing method as set forth in claim 11 , further comprising:
cumulatively storing the use time of the semiconductor device by programming one of an antifuse, an e-fuse or a flash memory cell.

14 . The use time managing method as set forth in claim 11 , wherein the cumulative use time is obtained by counting a number of auto-refresh commands and self-refresh commands.

15 . The use time managing method as set forth in claim 11 , wherein adjusting the operation of an internal circuit of the semiconductor device includes changing at least one of a voltage level, an amount of delay time and a driving capability.

16 . A semiconductor device comprising:
a measuring circuit configured to measure accumulated operation time of the semiconductor device by generating a plurality of storage activation signals, each corresponding to a predetermined amount of operation time of the semiconductor device; a storage circuit configured to cumulatively store data indicating occurrences of the generated storage activation signals; and a read circuit configured to read the cumulatively stored data such that use time of the semiconductor device is detected.

17 . The semiconductor device of claim 16 , further comprising:
a control circuit configured to generate adjusting information when the detected use time reaches a reference time value, wherein a voltage level or an amount of delay time of an internal circuit of the semiconductor device is adjusted based on the adjusting information.

18 . The semiconductor device of claim 16 , wherein the storage circuit includes at least one of an antifuse, an e-fuse and a flash memory cell.

19 . The semiconductor device of claim 16 , wherein the plurality of storage activation signals are generated by a frequency divider configured to divide a clock signal generated by a clock generator of the semiconductor device or by a counter configured to count a number of refresh commands.

20 . The semiconductor device of claim 19 , wherein the number of refresh commands includes a number of auto-refresh commands and self-refresh commands.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Jong-Pil
• Park Chul-Woo
• Sohn Young-Soo

Classifications

• G11C29/28

  Dependent multiple arrays, e.g. multi-bit arrays · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title