Method For Compensating Resistance Of Signal Lines Of Gate Driving Circuits And Liquid Crystal Panel Applying The Same
US-2015379951-A1 · Dec 31, 2015 · US
US2016104441A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016104441-A1 |
| Application number | US-201514864611-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 24, 2015 |
| Priority date | Oct 14, 2014 |
| Publication date | Apr 14, 2016 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A flat panel display includes a display panel comprising a display area and a non-display area which is disposed on a outside of the display area and has at least one recess on one end side thereof; a driving substrate disposed on a rear surface of the display panel; and at least one connection member connected to the display panel and the driving substrate through at least one recess.
Opening claim text (preview).
What is claimed is: 1 . A flat panel display comprising: a display panel comprising a display area and a non-display area which is disposed on an outside of the display area and has at least one recess on one end side thereof; a driving substrate disposed on a rear surface of the display panel; and at least one connection member connected to the display panel and the driving substrate through the at least one recess. 2 . The flat panel display of claim 1 , wherein the display panel comprises: a lower substrate comprising the display area having a thin film transistor (TFS) and the non-display area having the at least one recess; and an upper substrate disposed to correspond to the display area of the lower substrate. 3 . The flat panel display of claim 1 , wherein the at least one recess is formed by removing a predetermined area from the one end side of the non-display area of the display panel. 4 . The flat panel display of claim 1 , wherein the at least one recess comprises a horizontal side being spaced apart in parallel from the one end side of the non-display area, and at least one connection member is disposed between the one end side of the non-display area and the horizontal side. 5 . The flat panel display of claim 1 , wherein the at least one connection member passes through the at least one recess. 6 . The flat panel display of claim 1 , wherein the at least one connection member includes two or more connection members, and wherein the two or more connection members pass through the at least one recess.
Display panel composed of stacked panels · CPC title
using a passive matrix (G09G3/3674 - G09G3/3696 take precedence) · CPC title
Conductors connecting driver circuitry and terminals of panels · CPC title
characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title
Details of electrical connections of light sources to drivers, circuit boards, or the like · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.