Pipelined intra-prediction hardware architecture for video coding

Patent metadata

Field	Value
Publication number	US-2016100191-A1
Application number	US-201414503669-A
Country	US
Kind code	A1
Filing date	Oct 1, 2014
Priority date	Oct 1, 2014
Publication date	Apr 7, 2016
Grant date	—

Abstract

As the quality and quantity of shared video content increases, video encoding standards and techniques are being developed and improved to reduce bandwidth consumption over telecommunication and other networks. One technique to reduce bandwidth consumption is intra-prediction, which exploits spatial redundancies within video frames. Each video frame may be segmented into blocks, and intra-prediction may be applied to the blocks. However, intra-prediction of some blocks may rely upon the completion (e.g., reconstruction) of other blocks, which can make parallel processing challenging. Provided are exemplary techniques for improving the efficiency and throughput associated with the intra-prediction of multiple blocks.

First claim

What is claimed is:

1 . A method of performing intra-prediction, the method comprising:
receiving, at a neighbor processing unit, a first plurality of neighbor pixels; preparing, by the neighbor processing unit, the first plurality of neighbor pixels for intra-prediction by an intra-prediction processing unit; receiving, by the intra-prediction processing unit, the prepared first plurality of neighbor pixels; determining, by the intra-prediction processing unit, a first block having a first plurality of intra-predicted pixels using the prepared first plurality of neighbor pixels during a first time period; receiving, by the neighbor processing unit, a second plurality of neighbor pixels for intra-prediction of a second block; preparing, by the neighbor processing unit, the second plurality of neighbor pixels for intra-prediction during at least part of the first time period; and determining, by the intra-prediction processing unit, a second block having a second plurality of intra-predicted pixels using the prepared second plurality of neighbor pixels during a second time period immediately following the first time period, wherein at least some of the first plurality of intra-predicted pixels in the first block correspond with at least some of the second plurality of neighbor pixels used for determining the second block.

2 . The method of claim 1 , wherein the second time period is substantially immediately after the first time period.

3 . The method of claim 1 , wherein the preparing of the first plurality of neighbor pixels comprises padding and filtering the first plurality of neighbor pixels.

4 . The method of claim 1 , wherein the first and second blocks are transform blocks that are both associated with a common intra-prediction mode.

5 . The method of claim 1 , wherein the intra-prediction processing unit comprises a number, N, of processing engines, and wherein each processing engine intra-predicts a different pixel during each cycle of the first time period.

6 . The method of claim 5 , wherein the first block has a size of M pixels by M pixels, and wherein the first time period when the intra-prediction processing unit determines the first block lasts approximately M*M/N cycles.

7 . The method of claim 6 , wherein the preparing of the second plurality of neighbor cells begins approximately 2M/N cycles after the determining of the first block is finished.

8 . The method of claim 5 , wherein the neighbor processing unit receives the first and second pluralities of neighbor pixels from a neighbor buffer having a read bandwidth of 2N pixels per cycle.

9 . The method of claim 6 , wherein the first plurality of neighbor pixels comprises 4M+1 pixels.

10 . The method of claim 1 , wherein the determining of the first block comprises determining a critical row or column of intra-predicted pixels before determining a remainder of the first block, wherein the critical row or column of intra-predicted pixels corresponds with at least some of the second plurality of neighbor pixels used to determine the second block.

11 . A processor for performing intra-prediction, the processor comprising:
a neighbor processing unit operable to receive and prepare first and second pluralities of neighbor pixels for intra-prediction; and an intra-prediction processing unit operable to determine a first block having a first plurality of intra-predicted pixels using the prepared first plurality of neighbor pixels during a first time period, the intra-prediction processing unit further operable to determine a second block having a second plurality of intra-predicted pixels using the prepared second plurality of neighbor pixels during a second time period, wherein at least some of the first plurality of intra-predicted pixels in the first block correspond with at least some of the second plurality of neighbor pixels used for determining the second block; and wherein the neighbor processing unit is further operable to prepare the second plurality of neighbor pixels during at least part of the first time period.

12 . The processor of claim 11 , wherein the second time period is substantially immediately after the first time period.

13 . The processor of claim 11 , wherein the neighbor processing unit is further operable to pad and filter the first plurality of neighbor pixels.

14 . The processor of claim 11 , wherein the first and second blocks are transform blocks that are both associated with a common intra-prediction mode.

15 . The processor of claim 11 , wherein the intra-prediction processing unit comprises a number, N, of processing engines, and wherein each processing engine is operable to intra-predict a different pixel during each cycle of the first time period.

16 . The processor of claim 15 , wherein the first block has a size of M pixels by M pixels, and wherein the first time period lasts approximately M*M/N cycles.

17 . The processor of claim 16 , wherein the neighbor processing unit is operable to begin preparing the second plurality of neighbor cells approximately 2M/N cycles after the intra-prediction processing unit finishes determining the first block.

18 . The processor of claim 15 , further comprising a neighbor buffer operable to store the first and second pluralities of neighbor pixels, wherein the neighbor buffer has a read bandwidth of 2N pixels per cycle.

19 . The processor of claim 16 , wherein the first plurality of neighbor pixels comprises 4M+1 pixels.

20 . The processor of claim 11 , wherein the intra-prediction processing unit is further operable to determine a critical row or column of intra-predicted pixels in the first block before determining a remainder of the first block, wherein the critical row or column of intra-predicted pixels corresponds with at least some of the second plurality of neighbor pixels used to determine the second block.

21 . A video decoder, comprising:
an intra-prediction module operable to perform intra-prediction, the intra-prediction module comprising:
a neighbor processing unit operable to receive and prepare first and second pluralities of neighbor pixels for intra-prediction; and
an intra-prediction processing unit operable to determine a first block having a first plurality of intra-predicted pixels using the prepared first plurality of neighbor pixels during a first time period, the intra-prediction processing unit further operable to determine a second block having a second plurality of intra-predicted pixels using the prepared second plurality of neighbor pixels during a second time,
wherein the neighbor processing unit is further operable to prepare the second plurality of neighbor pixels during at least part of the first time period;
an inverse transform module operable to provide a first residual block and a second residual block; and a summer operable to add the first block with the first residual block to determine a first reconstructed block, the summer further operable to add the second block with the second residual block to determine a second reconstructed block, wherein the first reconstructed block comprises at least some of the second plurality of neighbor pixels used for determining the second block.

22 . The video decoder of claim 21 , further comprising:
a reference frame buffer operable to store the first and second reconstructed blocks as portions of a reference frame, wherein the reference frame may be used for at least one of subsequent motion compensation,

Assignees

• Qualcomm Inc

Inventors

• Mishra Ashish
• Mohanta Arindam

Classifications

• H04N19/146

  Data rate or code amount at the encoder output · CPC title

• H04N19/61 Primary

  in combination with predictive coding · CPC title

• H04N19/52 Primary

  by predictive encoding · CPC title

• H04N19/176

  the region being a block, e.g. a macroblock · CPC title

• H04N19/593 Primary

  involving spatial prediction techniques · CPC title