Coordination for one-sided memory access in a partitioned global address space

Patent metadata

Field	Value
Publication number	US-2016100010-A1
Application number	US-201414582240-A
Country	US
Kind code	A1
Filing date	Dec 24, 2014
Priority date	Oct 6, 2014
Publication date	Apr 7, 2016
Grant date	—

Abstract

Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator.

First claim

What is claimed is:

1 . A network interface controller comprising:
a transceiver module to receive a message over a network, said message comprising a data portion and a data size indicator; an offset handler module to calculate a destination address from a base address of a memory buffer and an offset counter; said transceiver module further to write said data portion to said memory buffer at said destination address; and said offset handler module further to update said offset counter based on said data size indicator.

2 . The controller of claim 1 , wherein said memory buffer is included in a local memory partition of a Partitioned Global Address Space.

3 . The controller of claim 2 , wherein said network interface controller and said local memory partition are included in a first processing element node of a High Performance Computing (HPC) system.

4 . The controller of claim 3 , wherein said message is generated by a second processing element node of said High Performance Computing (HPC) system.

5 . The controller of claim 1 , further comprising an interrupt handler to trigger an interrupt based on said received message, said interrupt to cause said offset handler module to initiate said destination address calculation and offset counter update.

6 . The controller of claim 1 , wherein said update of said offset counter is performed as an atomic operation.

7 . The controller of claim 1 , wherein said calculation of said destination address and said update of said offset counter are performed as an atomic operation.

8 . At least one computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations comprising:
receiving a message over a network, said message comprising a data portion and a data size indicator; calculating a destination address from a base address of a memory buffer and an offset counter; updating said offset counter based on said data size indicator; and writing said data portion to said memory buffer at said destination address.

9 . The computer-readable storage medium of claim 8 , wherein said memory buffer is included in a local memory partition of a Partitioned Global Address Space.

10 . The computer-readable storage medium of claim 9 , wherein said local memory partition is included in a first processing element node of a High Performance Computing (HPC) system.

11 . The computer-readable storage medium of claim 10 , wherein said message is generated by a second processing element node of said High Performance Computing (HPC) system.

12 . The computer-readable storage medium of claim 8 , further comprising triggering an interrupt based on said received message, said interrupt initiating said destination address calculation and said offset counter update.

13 . The computer-readable storage medium of claim 8 , further comprising performing said update of said offset counter as an atomic operation.

14 . The computer-readable storage medium of claim 8 , further comprising performing said calculation of said destination address and said update of said offset counter as an atomic operation.

15 . The computer-readable storage medium of claim 8 , further comprising providing an application programming interface to generate said message.

16 . A method comprising:
receiving a message over a network, said message comprising a data portion and a data size indicator; calculating a destination address from a base address of a memory buffer and an offset counter; updating said offset counter based on said data size indicator; and writing said data portion to said memory buffer at said destination address.

17 . The method of claim 16 , wherein said memory buffer is included in a local memory partition of a Partitioned Global Address Space.

18 . The method of claim 17 , wherein said local memory partition is included in a first processing element node of a High Performance Computing (HPC) system.

19 . The method of claim 18 , wherein said message is generated by a second processing element node of said High Performance Computing (HPC) system.

20 . The method of claim 16 , further comprising triggering an interrupt based on said received message, said interrupt initiating said destination address calculation and said offset counter update.

21 . The method of claim 16 , further comprising performing said update of said offset counter as an atomic operation.

22 . The method of claim 16 , further comprising performing said calculation of said destination address and said update of said offset counter as an atomic operation.

23 . The method of claim 16 , further comprising providing an application programming interface to generate said message.

Assignees

• Intel Corp

Inventors

• Flajslik Mario
• Dinan James

Classifications

• G06F12/0692

  Multiconfiguration, e.g. local and global addressing · CPC title

• H04L67/1097 Primary

  for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

• G06F12/0653

  with centralised address assignment · CPC title

• G06F2212/154

  Networked environment · CPC title