Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-2016086813-A1
Application number	US-201514708544-A
Country	US
Kind code	A1
Filing date	May 11, 2015
Priority date	Sep 24, 2014
Publication date	Mar 24, 2016
Grant date	—

Abstract

A method of fabricating a semiconductor device includes forming an active region in a semiconductor substrate, forming a plurality of dummy gates on the active region, the plurality of dummy gates having a gate mask disposed thereon, forming an interlayer insulating layer on the gate mask, and performing a one-time chemical mechanical polishing (CMP) process by using a slurry composition capable of polishing the interlayer insulating layer and the gate mask until top surfaces of the dummy gates are exposed.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
forming an active region in a semiconductor substrate; forming a plurality of dummy gates on the active region, the plurality of dummy gates having a gate mask disposed thereon; forming an interlayer insulating layer on the gate mask; and performing a one-time chemical mechanical polishing (CMP) process using a slurry composition capable of polishing the interlayer insulating layer and the gate mask until top surfaces of the dummy gates are exposed.

2 . The method of claim 1 , wherein
the forming a plurality of dummy gates forms the plurality of dummy gates having the gate mask including a silicon nitride layer disposed thereon, the forming a plurality of dummy gates forms the dummy gates including polysilicon, the forming an interlayer insulating layer forms the interlayer insulating layer including a silicon oxide layer, and the performing uses the slurry composition including a polishing agent, a silicon nitride layer polishing accelerator, a polysilicon layer polishing inhibitor, a silicon oxide layer polishing control agent, a pH control agent, and a remaining percentage by weight of solvent.

3 . The method of claim 1 , wherein the performing uses the slurry composition having a polishing selectivity for a silicon nitride layer to a silicon oxide layer ranging from about 1:1 to about 3:1.

4 . The method of claim 1 , wherein the performing uses the slurry composition having a polishing selectivity for a silicon nitride layer to a polysilicon layer ranging from about 50:1 to about 300:1.

5 . The method of claim 1 , wherein the performing uses the slurry composition having a polishing selectivity for a silicon oxide layer to a polysilicon layer ranging from about 30:1 to about 200:1.

6 . The method of claim 1 , wherein the semiconductor device includes a three-dimensional memory array.

7 . The method of claim 2 , wherein the performing uses the polishing agent including at least one of silica particles, alumina particles, ceria particles, zirconia particles, and titania particles.

8 . The method of claim 2 , wherein the performing uses the silicon nitride layer polishing accelerator including at least one of isoleucine, alanine, glycine, glutamine, threonine, serine, asparagine, tyrosine, cysteine, valine, and leucine.

9 . The method of claim 2 , wherein the performing uses the silicon nitride layer polishing accelerator having a content of about 0.01% by weight to about 10% by weight in the slurry composition.

10 . The method of claim 2 , wherein the performing uses the polysilicon layer polishing inhibitor including at least one of polyvinyl alcohol (PVA), ethylene glycol (EG), glycerine, polyethylene glycol (PEG), polypropylene glycol (PPG), polyvinyl pyrrolidone (PVP), poly(acrylic acid) (PAA), ammonium salts of PAA, poly(methacrylic acid) (PMAA), ammonium salts of PMAA, polyacrylic maleic acid, an alkyl sodium sulfonate fluorosurfactant, a polyoxyethylene fluorosurfactant, and a nonionic ethoxylated fluorosurfactant.

11 . The method of claim 2 , wherein the performing uses the polysilicon layer polishing inhibitor having a content of about 0.0001% by weight to about 1% by weight in the slurry composition.

12 . The method of claim 2 , wherein the performing uses the silicon oxide layer polishing control agent including at least one of 1-2-hydroxyethyl-2-pyrrolidone, 4-hydroxyethyl-2-pyrrolidone, maleic anhydride, maleic hydrazide, and malemide.

13 . The method of claim 2 , wherein the performing uses the silicon oxide layer polishing control agent having a content of about 0.01% by weight to about 10% by weight in the slurry composition.

14 . The method of claim 2 , wherein the performing uses the pH control agent including at least one of ammonia, ammonium methyl propanol (AMP), tetra methyl ammonium hydroxide (TMAH), potassium hydroxide, sodium hydroxide, magnesium hydroxide, rubidium hydroxide, cesium hydroxide, sodium bicarbonate, sodium carbonate, triethanolamine, tromethamine, niacinamide, nitric acid, sulphuric acid, phosphoric acid, hydrochloric acid, acetic acid, citric acid, glutaric acid, glycolic acid, formic acid, lactic acid, malic acid, malonic acid, maleic acid, oxalic acid, phthalic acid, succinic acid, and tartaric acid.

15 . A method of fabricating a semiconductor device, the method comprising:
forming an active region in a semiconductor substrate; forming a plurality of polysilicon layer patterns on the active region, the plurality of polysilicon layer patterns having a silicon nitride layer disposed thereon; forming a silicon oxide layer on the silicon nitride layer; and performing a one-time chemical mechanical polishing (CMP) process using a slurry composition to remove the silicon nitride layer and the silicon oxide layer until a top surface of the polysilicon layer patterns are exposed, the slurry composition containing a polishing agent, a silicon nitride layer polishing accelerator, a polysilicon layer polishing inhibitor, a silicon oxide layer polishing control agent, a pH control agent, and a remaining percentage by weight of solvent.

16 . A method of fabricating a semiconductor device, the method comprising:
forming a plurality of poly-Si patterns on a semiconductor substrate; forming a silicon nitride layer on the plurality of poly-Si patterns; forming a silicon oxide layer covering the silicon nitride layer and the semiconductor substrate; and
performing a chemical mechanical polishing (CMP) process using a slurry composition to remove the silicon nitride layer and the silicon oxide layer until top surfaces of the plurality of poly-Si patterns are exposed, the slurry composition having a higher polishing selectivity for the silicon nitride layer and the silicon oxide layer than for the poly-Si patterns.

17 . The method of claim 16 , wherein the performing uses the slurry composition including a polishing agent, a silicon nitride layer polishing accelerator, a polysilicon layer polishing inhibitor, a silicon oxide layer polishing control agent, a pH control agent, and a remaining percentage by weight of solvent.

18 . The method of claim 16 , wherein the performing uses the slurry composition having the polishing selectivity for the silicon nitride layer to the silicon oxide layer ranging from about 1:1 to about 3:1.

19 . The method of claim 16 , wherein the performing uses the slurry composition having the polishing selectivity for the silicon nitride layer to the poly-Si patterns ranging from about 50:1 to about 300:1.

20 . The method of claim 16 , wherein the performing uses the slurry composition having the polishing selectivity for the silicon oxide layer to the poly-Si patterns ranging from about 30:1 to about 200:1.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ye-Hwan
• Paik Un-Gyu
• Seo Ji-Hoon
• Kim Sang-Kyun
• Kim Jong-Woo
• Lee Dong-Jun

Classifications

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L21/823437

  Electricity · mapped topic