Solid-state imaging device, drive method thereof and camera system

Patent metadata

Field	Value
Publication number	US-2016080616-A1
Application number	US-201514690952-A
Country	US
Kind code	A1
Filing date	Apr 20, 2015
Priority date	Apr 28, 2010
Publication date	Mar 17, 2016
Grant date	—

Abstract

A solid-state imaging device includes: pixel signal reading lines; a pixel unit in which pixels including photoelectric conversion elements are arranged; and a pixel signal reading unit performing reading of pixel signals from the pixel unit through the pixel signal reading lines, wherein the pixel signal reading unit includes current source circuits each of which includes a load element as a current source connected to the pixel signal reading line forming a source follower, and the current source circuit includes a circuit generating electric current according to a slew rate of the pixel signal reading line and replicating electric current corresponding to the above electric current to flow in the current source.

First claim

What is claimed is:

1 . A solid-state imaging device comprising:
a drain of a replica circuit transistor directly electrically connected to a drain of a first transistor; an electrode of a capacitor directly electrically connected to a source of the replica circuit transistor, a source of a load transistor directly electrically connected to a source of the first transistor; a vertical signal line directly electrically connected to a drain of the load transistor; a gate of the first transistor directly electrically connected to said drain of the first transistor; a gate of the load transistor directly electrically connected to said gate of the first transistor.

2 . The solid-state imaging device according to claim 1 , wherein said first transistor is of a first conductive type, said replica circuit transistor being of a second conductive type.

3 . The solid-state imaging device according to claim 1 , wherein said first transistor and said load transistor are of a same conductive type.

4 . The solid-state imaging device according to claim 1 , wherein said load transistor is an NMOS transistor.

5 . The solid-state imaging device according to claim 1 , wherein said first transistor is an NMOS transistor, said replica circuit transistor being of a PMOS transistor.

6 . The solid-state imaging device according to claim 1 , further comprising:
a selection transistor configurable to provide an electrical connection and disconnection between an amplifier transistor and said vertical signal line.

7 . The solid-state imaging device according to claim 6 , further comprising:
a floating diffusion directly electrically connected to a gate of the amplifier transistor.

8 . The solid-state imaging device according to claim 7 , further comprising:
a reset transistor configurable to provide an electrical connection and disconnection between a power supply line and said floating diffusion.

9 . The solid-state imaging device according to claim 7 , further comprising:
a transfer transistor configurable to provide an electrical connection and disconnection between a photoelectric conversion element and said floating diffusion.

10 . The solid-state imaging device according to claim 1 , further comprising:
a gate of the replica circuit transistor directly electrically connected to said vertical signal line.

11 . The solid-state imaging device according to claim 1 , further comprising:
a gate of the replica circuit transistor directly electrically connected to a source of a second transistor and to a drain of a third transistor.

12 . The solid-state imaging device according to claim 11 , wherein said first transistor and said second transistor are of a same conductive type.

13 . The solid-state imaging device according to claim 11 , wherein said first transistor and said third transistor are of a same conductive type.

14 . The solid-state imaging device according to claim 11 , wherein said second transistor and said third transistor are of a same conductive type.

15 . The solid-state imaging device according to claim 11 , further comprising:
a gate of the second transistor directly electrically connected to said vertical signal line.

16 . The solid-state imaging device according to claim 11 , further comprising:
a source of the third transistor directly electrically connected to said source of the first transistor.

17 . The solid-state imaging device according to claim 11 , further comprising:
a gate of the third transistor directly electrically connected to a bias power supply.

18 . The solid-state imaging device according to claim 1 , further comprising:
a current source directly electrically connected to said source of the replica circuit transistor.

19 . The solid-state imaging device according to claim 1 , further comprising:
another electrode of the capacitor directly electrically connected to a reference potential.

20 . The solid-state imaging device according to claim 19 , wherein said source of the load transistor and said source of the first transistor are directly electrically connected to said reference potential.

21 . A camera system comprising:
the solid-state imaging device according to claim 1 ; an optical system configured to direct incident light onto said solid-state imaging device.

Assignees

• Sony Corp

Inventors

• Gendai Yuji
• Toyomura Junji
• Kanagawa Norifumi

Classifications

• H04N25/00 Primary

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N23/54 Primary

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N5/2253 Primary

  Electricity · mapped topic

• H04N25/671

  for non-uniformity detection or correction · CPC title