Method and device for an integrated trench capacitor

Patent metadata

Field	Value
Publication number	US-2016079342-A1
Application number	US-201514948587-A
Country	US
Kind code	A1
Filing date	Nov 23, 2015
Priority date	Jan 15, 2014
Publication date	Mar 17, 2016
Grant date	—

Abstract

A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.

First claim

What is claimed is:

1 . A device comprising:
a polymer block on a front surface of an interposer wafer; and a capacitor formed on an upper surface of and in one or more trenches in the polymer block.

2 . The device according to claim 1 , wherein the capacitor further comprises:
a first metal layer in the one or more trenches and on the upper surface of the polymer block.

3 . The device according to claim 2 , wherein the first metal layer is pulled back from outer edges of the polymer block.

4 . The device according to claim 2 , further comprising:
a dielectric layer on the first metal layer and side surfaces of the polymer block.

5 . The device according to claim 3 , further comprising:
a connection pad on the interposer wafer; and a second metal layer on the connection pad and on the dielectric layer.

6 . The device according to claim 1 , wherein the one or more trenches comprise one or more holes or one or more troughs in the polymer block.

7 . The device according to claim 1 , wherein the one or more trenches have an aspect ratio of 1:20 to 1:25.

8 . The device according to claim 1 , wherein the polymer layer is formed to a thickness of up to 100 micrometers (μm).

9 . The device according to claim 5 , wherein the first and second metal layers each have a thickness of 100 to 500 nm.

10 . The device according to claim 9 , wherein the first and second metal layers comprise copper (Cu) or aluminum (Al).

11 . A device comprising:
a polymer block on a front surface of an interposer wafer; a first metal layer formed in one or more trenches in the polymer block; a dielectric layer formed over the first metal layer; and a capacitor formed on an upper surface of and in the one or more trenches.

12 . The device according to claim 11 , wherein the first metal layer is pulled back from outer edges of the polymer block.

13 . The device according to claim 12 , wherein the dielectric layer is formed on the first metal layer and side surfaces of the polymer block.

14 . The device according to claim 13 , further comprising:
a connection pad on the interposer wafer; and a second metal layer on the connection pad and on the dielectric layer.

15 . The device according to claim 11 , wherein the one or more trenches comprise one or more holes or one or more troughs in the polymer block.

16 . The device according to claim 11 , wherein the one or more trenches have an aspect ratio of 1:20 to 1:25.

17 . The device according to claim 11 , wherein the polymer layer is formed to a thickness of up to 100 micrometers (μm).

18 . The device according to claim 14 , wherein the first and second metal layers each have a thickness of 100 to 500 nm.

19 . The device according to claim 18 , wherein the first and second metal layers comprise copper (Cu) or aluminum (Al).

20 . A device comprising:
a polymer block on a front surface of an interposer wafer; a first metal layer formed in trenches in the polymer block; a dielectric layer formed over the first metal layer; a second metal layer on the dielectric layer; and a capacitor formed on an upper surface of and in the trenches, wherein the trenches have an aspect ratio of 1:20 to 1:25.

Assignees

• Globalfoundries Inc

Inventors

• England Luke

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10D1/716

  having vertical extensions · CPC title