Programmable electrical fuse in keep out zone

Patent metadata

Field	Value
Publication number	US-2016079166-A1
Application number	US-201414483258-A
Country	US
Kind code	A1
Filing date	Sep 11, 2014
Priority date	Sep 11, 2014
Publication date	Mar 17, 2016
Grant date	—

Abstract

An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

First claim

1 . A method comprising:
forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion comprising a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material; forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion; forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via; and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

2 . The method of claim 1 , wherein forming an electronic fuse in the BEOL wiring portion comprises:
forming a fuse link, a first electrode, and a second electrode, the fuse link is formed in the plurality of layers of the metallic material and the dielectric material.

3 . The method of claim 1 , wherein forming the electronic fuse in the BEOL wiring portion comprises:
forming a fuse link, a first electrode, and a second electrode, the second electrode is electrically coupled to the guard ring.

4 . The method of claim 1 , wherein forming the electronic fuse in the BEOL wiring portion comprises:
forming a fuse link, a first electrode, and a second electrode, the first electrode and the second electrode are electrically independent from both the guard ring and the through-substrate via.

5 . The method of claim 1 , wherein forming the electronic fuse in the BEOL wiring portion comprises:
forming a fuse link, a first electrode, and a second electrode, the first electrode is electrically coupled to the through-substrate via.

6 . The method of claim 1 , wherein forming the electronic fuse in the BEOL wiring portion comprises:
forming a fuse link, a first electrode, and a second electrode, each comprising a plurality of solid metallic portions stacked in the BEOL wiring portion such that the electronic fuse is a continuous metallic structure.

7 . The method of claim 1 , wherein the guard ring is spaced apart from the electronic fuse, the guard ring is spaced apart from the through-substrate via, and the electronic fuse is spaced apart from the through-substrate via.

8 . A method comprising:
forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion comprising a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material; forming a first opening in the BEOL wiring portion; forming a second opening in the BEOL wiring portion adjacent to and surrounded by the first opening, the first opening and the second opening being separated by a distance; filling the first opening with a material to form a guard ring; filling the second opening with the material to form an electronic fuse; forming a through-substrate via opening through the BEOL wiring portion and the semiconductor base portion, the through-substrate via opening being surrounded entirely by the guard ring, the through silicon via opening through the semiconductor base portion being free of the guard ring; and depositing metallization in the through silicon via opening to form a through silicon via.

9 . The method of claim 8 , wherein filling the second opening with the material to form an electronic fuse comprises:
forming a fuse link, a first electrode, and a second electrode, the fuse link is formed in plurality of layers of the metallic material and the dielectric material immediately above the semiconductor base portion.

10 . The method of claim 8 , wherein the electronic fuse is electrically connected to the guard ring.

11 . The method of claim 8 , wherein the electronic fuse is electrically independent from the guard ring and the through-substrate via.

12 . The method of claim 8 , wherein the electronic fuse is electrically connected to the through-substrate via.

13 . The method of claim 9 , wherein the electronic fuse and the guard ring each comprise a plurality of solid metallic portions stacked in the BEOL wiring portion such that the electronic fuse and the guard ring are each a continuous metallic structure.

14 . A structure comprising:
a semiconductor base portion comprising a semiconductor material; a back end of the line (BEOL) wiring portion directly on top of the semiconductor base portion, the BEOL wiring portion comprising a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material; a through-substrate via extending through the BEOL wiring portion and the semiconductor base portion; an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, the electronic fuse and the through-substrate via are separated by a distance; and a guard ring in the BEOL wiring portion surrounding both the through-substrate via and the electronic fuse, the through-substrate via in the semiconductor base portion being free from the guard ring.

15 . The structure of claim 14 , wherein the electronic fuse comprises a fuse link, a first electrode, and a second electrode, and the fuse link is in plurality of layers of the metallic material and the dielectric material.

16 . The structure of claim 14 , wherein the electronic fuse comprises a fuse link, a first electrode, and a second electrode, and the second electrode is electrically coupled to the guard ring.

17 . The structure of claim 14 , wherein the electronic fuse comprises a fuse link, a first electrode, and a second electrode, and the first electrode and the second electrode are electrically independent of both the guard ring and the through-substrate via.

18 . The structure of claim 14 , wherein the electronic fuse comprises a fuse link, a first electrode, and a second electrode, and the first electrode is electrically coupled to the through-substrate via.

19 . The structure of claim 14 , wherein the electronic fuse comprises a fuse link, a first electrode, and a second electrode each comprising a plurality of solid metallic portions stacked in the BEOL wiring portion such that the electronic fuse is a continuous metallic structure.

20 . The structure of claim 14 , wherein the guard ring is spaced apart from the electronic fuse, the guard ring is spaced apart from the through-substrate via, and the electronic fuse is spaced apart from the through-substrate via.

Assignees

• IBM

Inventors

• Farooq Mukta G
• Sullivan Timothy D
• Wang Ping-Chuan
• Zhang Lijuan

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L23/481

  Electricity · mapped topic