Method for fabricating crystalline photovoltaic cells

Patent metadata

Field	Value
Publication number	US-2016072001-A1
Application number	US-201514839785-A
Country	US
Kind code	A1
Filing date	Aug 28, 2015
Priority date	Sep 4, 2014
Publication date	Mar 10, 2016
Grant date	—

Abstract

A method for fabricating a crystalline semiconductor photovoltaic cell is disclosed. In one aspect, the method includes depositing a dielectric layer at first predetermined locations on a surface of a semiconductor substrate. The method further includes growing a doped epitaxial layer at second predetermined locations on a surface of the semiconductor substrate, the second predetermined locations being different from and non-overlapping with the first predetermined locations. The method further includes maintaining the dielectric layer as a surface passivation layer in the photovoltaic cell. The method also includes forming an emitter region, a back surface field region or a front surface field region of the photovoltaic cell from the doped epitaxial layer.

First claim

What is claimed is:

1 . A method for fabricating a crystalline semiconductor photovoltaic cell, the method comprising:
depositing a dielectric layer at first predetermined locations on a surface of a semiconductor substrate; and growing a doped epitaxial layer at second predetermined locations on a surface of the semiconductor substrate, the second predetermined locations being different from and non-overlapping with the first predetermined locations, wherein the dielectric layer remains on the surface of the semiconductor substrate during fabrication of the photovoltaic cell, and wherein the dielectric layer is maintained as a surface passivation layer of the photovoltaic cell.

2 . The method of claim 1 , wherein the dielectric layer is deposited at a temperature lower than 500° C.

3 . The method of claim 1 , wherein depositing the dielectric layer at the first predetermined locations comprises depositing the dielectric layer by chemical vapor deposition, atomic layer deposition, pyrolytic coating, spin coating, spray coating or dip coating.

4 . The method of claim 1 , wherein the dielectric layer comprises silicon oxide, silicon nitride, silicon carbide, oxynitride or titanium oxide.

5 . The method of claim 1 , wherein growing the doped epitaxial layer comprises growing the doped epitaxial layer at a temperature in the range between 600° C. and 1000° C.

6 . The method of claim 1 , wherein the doped epitaxial layer forms an emitter region, a back surface field region and/or a front surface field region of the photovoltaic cell.

7 . The method of claim 1 , wherein the first predetermined locations and the second predetermined locations are present on a same surface of the semiconductor substrate.

8 . The method of claim 1 , wherein the first predetermined locations and the second predetermined locations are present on opposite surfaces of the semiconductor substrate.

9 . The method of claim 1 , wherein the first predetermined locations are present on both surfaces of the semiconductor substrate.

10 . The method of claim 1 , wherein the second predetermined locations are present on both surfaces of the semiconductor substrate.

11 . The method according to claim 1 , wherein depositing the dielectric layer at the first predetermined locations comprises depositing the dielectric layer at the first predetermined locations and at the second predetermined locations, followed by removing the dielectric layer from the second predetermined locations.

12 . The method according to claim 1 , wherein growing the doped epitaxial layer at the second predetermined locations comprises exposing both surfaces of the semiconductor substrate surfaces to a precursor, the precursor used during epitaxial growth.

Assignees

• Imec Vzw

Inventors

• Payo Maria Recaman
• Duerinckx Filip
• Aleman Monica

Classifications

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title

• H10F77/311

  for photovoltaic cells · CPC title

• H10F10/146

  Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side · CPC title

• H10F10/14

  Photovoltaic cells having only PN homojunction potential barriers · CPC title

• H10F71/129

  Passivating · CPC title