Multi iq-path synchronization

Patent metadata

Field	Value
Publication number	US-2016056987-A1
Application number	US-201414465768-A
Country	US
Kind code	A1
Filing date	Aug 21, 2014
Priority date	Aug 21, 2014
Publication date	Feb 25, 2016
Grant date	—

Abstract

Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.

First claim

What is claimed is:

1 . A method for handling a modulated signal for a wireless device, the method comprising:
receiving a clock signal; generating a first sync enable signal and a second sync enable signal based on an even edge of the clock signal, wherein the generating of the first sync enable signal comprise:
generating, by a first D Flip-Flop (DFF), a divided clock signal based on the clock signal;
generating, by a second DFF, a first output signal based on the divided clock signal from the first DFF;
generating, by a third DFF, a second output signal based on the divided clock signal and the first output signal from the second DFF; and
generating, by a fourth DFF, the first sync enable signal based on the clock signal and the second output signal from the third DFF;
generating, by a first divider having a first initial operating condition, a first IQ path comprising a first I component signal and a first Q component signal based on the first sync enable signal; and generating, by a second divider having a second initial operating condition, a second IQ path comprising a second I component signal and a second Q component signal based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.

2 . The method of claim 1 , further comprising:
receiving, by the first divider from a control circuit, a first enable signal, wherein the first divider only generates the first IQ path when it receives the first enable signal and the first sync enable signal; and receiving, by the second divider from a control circuit, a second enable signal, wherein the second divider only generates the second IQ path when it receives the second enable signal and the second sync enable signal.

3 . The method of claim 2 , further comprising:
powering the first divider after receiving the first sync enable signal; and powering the second divider after receiving the second sync enable signal.

4 . The method of claim 3 , wherein the control circuit generates a control signal to power the first or second divider.

5 . The method of claim 2 , wherein the first output signal is generated further based on the first enable signal.

6 . The method of claim 1 , further comprising:
modulating, by a first transmitter, a first data signal using the first IQ path; and modulating, by a second transmitter, a second data signal using the second IQ path.

7 . The method of claim 6 , further comprising:
transmitting, by a first antenna, the modulated first data signal received from the first transmitter; and transmitting, by a second antenna, the modulated second data signal received from the second transmitter.

8 . The method of claim 1 , further comprising:
modulating, by a transmitter, a first data signal using the first IQ path; and demodulating, by a receiver, a second data signal using the second IQ path.

9 . The method of claim 1 , further comprising:
generating, for each of a plurality of dividers, a sync enable signal based on an even edge of the clock signal, wherein each of the plurality of dividers have an initial operating condition; and generating, by each of the plurality of dividers, an IQ path based on the sync enable signal generated for the divider, wherein the initial operating condition of the plurality of dividers are not all equal.

10 . The method of claim 1 , wherein the first divider comprises a binary divider circuit comprising at least one edge-triggered D flip-flop, and further wherein the second divider comprises a binary divider circuit comprising at least one edge-triggered D flip-flop.

11 . A wireless apparatus for handling a modulated signal, the apparatus comprising:
a frequency generator that produces a clock signal; a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, the first synchronization circuit comprising:
a first D Flip-Flop (DFF) that receives the clock signal and generates a divided clock signal;
a second DFF that receives the divided clock signal and generates a first output signal;
a third DFF that receives the divided clock signal and the first output signal and generates a second output signal; and
a fourth DFF that receives the clock signal and the second output signal and generates the first sync enable signal;
a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal; a first divider having a first initial operating condition that generates a first IQ path comprising a first I component signal and a first Q component signal based on the first sync enable signal; and a second divider having a second initial operating condition that generates a second IQ path comprising a second I component signal and a second Q component signal based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.

12 . The apparatus of claim 11 , further comprising:
a control circuit that generates a first enable signal for the first divider and a second enable signal for the second divider, wherein the first divider only generates the first IQ path when it receives the first enable signal and the first sync enable signal and further wherein the second divider only generates the second IQ path when it receives the second enable signal and the second sync enable signal.

13 . The apparatus of claim 12 , wherein the first divider is powered after receiving the first sync enable signal and the second divider is powered after receiving the second sync enable signal.

14 . The apparatus of claim 13 , wherein the control circuit generates a control signal to power the first or second divider.

15 . The apparatus of claim 12 , wherein the second DFF further receives the first enable signal to generate the first output signal.

16 . The apparatus of claim 11 , further comprising:
a first transmitter that modulates a first data signal using the first IQ path; and a second transmitter that modulates a second data signal using the second IQ path.

17 . The apparatus of claim 16 , further comprising:
a first antenna that transmits the modulated first data signal received from the first transmitter; and a second antenna that transmits the modulated second data signal received from the second transmitter.

18 . The apparatus of claim 11 , further comprising:
a transmitter that modulates a first data signal using the first IQ path; and a receiver that demodulates a second data signal using the second IQ path.

19 . The apparatus of claim 11 , further comprising:
a plurality of dividers, each of the plurality of dividers having an initial operating condition; and a plurality of synchronization circuits, each of the plurality of synchronization circuits generating a sync enable signal based on an even edge of the clock signal, wherein each of the plurality of dividers generates an IQ path based on the sync enable signal generated for the divider, and further wherein for the initial operating conditions of the plurality of dividers are not all equal.

20 . The apparatus of claim 11 , wherein the first divider comprises a binary divider circuit comprising at least one edge-triggered D flip-flop, and further wherein the second divider comprises a binary divider circuit comprising at least one edge-triggered D flip-flop.

Assignees

• Qualcomm Inc

Inventors

• Choi Kiyong
• Yang Jeongsik
• Ko Jin-Su
• Zeng Yi

Classifications

• H04L27/2627

  Modulators · CPC title

• H04W56/0035 Primary

  detecting errors in frequency or phase · CPC title

• H04L27/2649

  Demodulators · CPC title

• H04L27/2662 Primary

  Symbol synchronisation · CPC title