Data distribution among multiple managed memories

Patent metadata

Field	Value
Publication number	US-2016048327-A1
Application number	US-201414459958-A
Country	US
Kind code	A1
Filing date	Aug 14, 2014
Priority date	Aug 14, 2014
Publication date	Feb 18, 2016
Grant date	—

Abstract

A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.

First claim

What is claimed is:

1 . A method for storing data in a data subsystem including a plurality of memory devices, wherein a coprocessor is coupled to a first memory device of the plurality of memory devices, the method comprising:
receiving a first plurality of data blocks; storing successive data blocks of the first plurality of data blocks in an interleaved pattern across each one of the plurality of memory devices; receiving a second plurality of data blocks, wherein each data block of the first plurality of data blocks and each data block of the second plurality of data blocks are of equal size; and storing successive data blocks of the second plurality of data blocks in contiguous storage locations of the first memory device responsive to a determination that the second data is to be accessed by the coprocessor.

2 . The method of claim 1 , wherein data stored in the first memory device includes at least one data block of the first plurality of data blocks, and at least two data blocks of the second plurality of data blocks.

3 . The method of claim 1 , wherein storing the successive data blocks of the first plurality of data blocks in an interleaved pattern across each one of the plurality of memory devices comprises storing each data block of a first contiguous subset of the first plurality of data blocks in a respective one of the plurality of memory devices before storing each data block of a second contiguous subset of the first plurality of data blocks in a respective one of the plurality of memory devices.

4 . The method of claim 1 , further comprising storing additional data blocks of the second plurality of data blocks in a second memory device of the plurality of memory devices responsive to a determination that the first memory device cannot store further data blocks of the second plurality of data blocks.

5 . The method of claim 2 , wherein the first memory device includes a plurality of memory dies.

6 . The method of claim 5 , wherein the at least one data block is stored in a first memory die of the plurality of memory dies, and the at least two data blocks are stored in a second memory die of the plurality of memory dies.

7 . The method of claim 1 , further comprising allocating a pre-determined amount of data of the first memory device for storing data that is to be accessed by the coprocessor.

8 . An apparatus, comprising:
a plurality of memory devices; a coprocessor coupled to a first memory device of the plurality of memory devices; and a processor coupled to each memory device of the plurality of memory devices, wherein the processor is configured to:
receive a first plurality of data blocks;
store successive data blocks of the first plurality of data blocks in an interleaved pattern across each one of the plurality of memory devices;
receive a second plurality of data blocks, wherein each data block of the first plurality of data blocks and each data block of the second plurality of data blocks are of equal size; and
store successive data blocks of the second plurality of data blocks in contiguous storage locations in the first memory device responsive to a determination that the second data is to be accessed by the coprocessor.

9 . The apparatus of claim 8 , wherein data stored in the first memory device includes at least one data block of the first plurality of data blocks, and at least two data blocks of the second plurality of data blocks.

10 . The apparatus of claim 8 , wherein to store the successive data blocks of the first plurality of data blocks in an interleaved pattern across each one of the plurality of memory devices, the processor is further configured to store each data block of a first contiguous subset of the first plurality of data blocks in a respective one of the plurality of memory devices before storing each data block of a second contiguous subset of the first plurality of data blocks in a respective one of the plurality of memory devices.

11 . The apparatus of claim 8 , wherein the processor is further configured to store additional data blocks of the second plurality of data blocks in a second memory device of the plurality of memory devices responsive to a determination that the first memory device cannot store further data blocks of the second plurality of data blocks.

12 . The apparatus of claim 9 , wherein the first memory device includes a plurality of memory dies, and wherein the at least one data block is stored in a first memory die of the plurality of memory dies, and the at least two data blocks are stored in a second memory die of the plurality of memory dies.

13 . The apparatus of claim 8 , wherein the coprocessor is configured to:
receive a third plurality of data blocks; and store data blocks of the third plurality of data blocks in contiguous storage locations of the first memory device.

14 . The apparatus of claim 8 , wherein the processor is further configured to allocate a pre-determined amount of storage locations of the first memory device for storing data that is to be accessed by the coprocessor.

15 . A computer-accessible non-transitory storage medium having program instructions stored therein that, in response to execution by a processor, cause the processor to perform operations comprising:
receiving a first plurality of data blocks; storing successive data blocks of the first plurality of data blocks in an interleaved pattern across each one of a plurality of memory devices; receiving a second plurality of data blocks, wherein each data block of the first plurality of data blocks and each data block of the second plurality of data blocks are of equal size; and storing successive data blocks of the second plurality of data blocks in contiguous storage locations of a first memory device responsive to a determination that the second data is to be accessed by a coprocessor coupled to the first memory device.

16 . The computer-accessible non-transitory storage medium of claim 15 , wherein data stored in the first memory device includes at least one data block of the first plurality of data blocks, and at least two data blocks of the second plurality of data blocks.

17 . The computer-accessible non-transitory storage medium of claim 15 , wherein storing the successive data blocks of the first plurality of data blocks in an interleaved pattern across each one of the plurality of memory devices comprises storing each data block of a first contiguous subset of the first plurality of data blocks in a respective one of the plurality of memory devices before storing each data block of a second contiguous subset of the first plurality of data blocks in a respective one of the plurality of memory devices.

18 . The computer-accessible non-transitory storage medium of claim 15 , further comprising storing additional data blocks of the second plurality of data blocks in a second memory device of the plurality of memory devices responsive to a determination that the first memory device cannot store further data blocks of the second plurality of data blocks.

19 . The computer-accessible non-transitory storage medium of claim 16 , wherein storing the successive data blocks of the first plurality of data blocks in the interleaved pattern across each one of the plurality of memory devices comprises storing the at least one data block of the first plurality of data blocks in a first memory die of a plurality of memory dies of the first memory device.

20 . The computer-accessible non-transitory storage medium of claim 1

Assignees

• Advanced Micro Devices Inc

Inventors

• Jayasena Nuwan S
• Hsu Lisa R
• O'Connor James M

Classifications

• G06F13/1647

  with interleaved bank access · CPC title

• G06F13/1657 Primary

  Access to multiple memories · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F2003/0692

  Physics · mapped topic