Wideband low-power amplifier

Patent metadata

Field	Value
Publication number	US-2016020740-A1
Application number	US-201414335421-A
Country	US
Kind code	A1
Filing date	Jul 18, 2014
Priority date	Jul 18, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

An amplifier is provided that includes a differential pair of transistors configured to steer a tail current responsive to a differential input voltage. The amplifier also includes a transconductor that tranconducts high-frequency changes in the differential output voltage into a differential bias current conducted through the differential pair of transistors.

First claim

We claim:

1 . A circuit, comprising:
a differential pair of transistors configured to steer a tail current responsive to a differential input voltage; a pair of load resistors configured to conduct a portion of the tail current; a differential high-pass filter configured to filter a differential output voltage defined across a pair of output terminals for the differential pair of transistors to produce a high-pass filtered differential voltage; and a transconductor configured to drive a differential bias current through the differential pair of transistors responsive to high-frequency changes in the differential input voltage.

2 . The circuit of claim 1 , wherein the pair of load resistors comprises:
a first load resistor coupled to a first one of the output terminals; and a second load resistor coupled to a remaining second one of the output terminals.

3 . The circuit of claim 1 , wherein a first transistor in the differential pair includes a first one of the output terminals and a second transistor in the differential pair includes a second one of the output terminals, and wherein the transconductor comprises a first plurality of transconductor transistors coupled to the first transistor's output terminal and a second plurality of transconductor transistors coupled to the second transistor's output terminal.

4 . The circuit of claim 3 , further comprising a first plurality of switches corresponding to the first plurality of transconductor transistors, wherein each transconductor transistor in the first plurality of transconductor transistors couples to a power supply node through the corresponding switch in the first plurality of switches.

5 . The circuit of claim 4 , wherein the first plurality of switches comprise a plurality of switching transistors having their gates controlled by an enable word.

6 . The circuit of claim 5 , further comprising a third plurality of transconductor transistors coupled to the first transistor's output terminal and a second plurality of switching transistors corresponding to the third plurality of transconductor transistors, wherein each transconductor transistor in the third plurality of transconductor transistors couples to the power supply node through a corresponding switching transistor in the second plurality of switching transistors, and wherein the second plurality of switching transistors are configured to have their gates controlled by a complement of the enable word.

7 . The circuit of claim 1 , wherein a first transistor in the differential pair includes a second terminal and a second transistor in the differential pair includes a second terminal, the circuit further comprising:
a first current source coupled to the first transistor's second terminal; and a second current source coupled to the second transistor's second terminal.

8 . The circuit of claim 7 , wherein the first transistor and the second transistor are each NMOS transistors, and wherein the second terminals are source terminals.

9 . The circuit of claim 7 , further comprising:
a variable resistor coupled between the second terminals; and a variable capacitor coupled between the second terminals.

10 . The circuit of claim 9 , wherein the variable resistor comprises a pair of variable resistors, and wherein the variable capacitor comprises a pair of variable capacitors.

11 . The circuit of claim 1 , wherein the transconductor comprises a first plurality of PMOS transistors coupled to a first one of the output terminals and a second plurality of PMOS transistors coupled to a second one of the output terminals.

12 . The circuit of claim 11 , wherein the differential high-pass filter comprises a first high-pass filter coupled between the first one of the output terminals and the gates for the second plurality of PMOS transistors.

13 . The circuit of claim 12 , wherein the differential high-pass filter further comprises a second high-pass filter coupled between the second one of the output terminals and the gates for the first plurality of PMOS transistors.

14 . A method, comprising:
steering a tail current through a differential pair of transistors responsive to a differential input voltage to produce a differential output voltage, high-pass filtering the differential output voltage to produce a high-pass filtered differential voltage; and transconducting the high-pass filtered differential voltage into a differential bias current conducted through the differential pair of transistors.

15 . The method of claim 14 , wherein steering the tail current comprises steering the tail current through a differential pair of NMOS transistors.

16 . The method of claim 14 , further comprising:
selecting from a plurality of transconducting transistors, wherein transconducting the high-pass filtered differential voltage comprises transconducting the high-pass filtered differential voltage using the selected transconducting transistors.

17 . The method of claim 16 , wherein selecting from the plurality of transconducting transistors comprises selecting a number of transconducting transistors sufficient to provide a desired amount of bandwidth extension, the method further comprising
biasing the differential pair with a selected number of biasing transconductor transistors, the selected number being complementary to the number of the selected transconducting transistors.

18 . The method of claim 14 , further comprising adjusting a variable resistance for a variable resistor coupled to a pair of second terminals for the differential pair of transistors to adjust a gain for the differential output voltage as compared to the differential input voltage.

19 . The method of claim 14 , further comprising adjusting a variable capacitance for a variable resistor coupled to a pair of second terminals for the differential pair of transistors to adjust a gain for the differential output voltage voltage as compared to the differential input voltage.

20 . A circuit, comprising:
a differential pair of transistors configured to steer a tail current responsive to a differential input voltage to produce a differential output voltage across a pair of output terminals for the differential pair of transistors; a pair of load resistors coupled to the pair of output terminals; a differential high-pass filter configured to filter the differential output voltage into a high-pass filtered differential voltage; and means for increasing a gain responsive to the high-pass filtered differential voltage, wherein the gain is defined by a ratio of the differential output voltage to the differential input voltage.

21 . The circuit of claim 20 , wherein the differential pair of transistors comprises a pair of NMOS transistors, and wherein the output terminals comprise drains for the pair of NMOS transistors.

22 . The circuit of claim 21 , further comprising:
a first current source coupled to a source for a first one of the NMOS transistors; and a second current source coupled to a source for a remaining second one of the NMOS transistors.

23 . The circuit of claim 21 , wherein a first one of the load resistors is coupled to the drain for the first NMOS transistor, and wherein a second one of the load resistors is coupled to the drain of the second NMOS transistor.

24 . The circuit of claim 21 , further comprising a variable resistor coupled between a source of a first one of the NMOS transistors and a source for

Assignees

• Qualcomm Inc

Inventors

• Arcudia Kenneth Luis
• Chen Zhiqin

Classifications

• H03F2203/45726

  the LC comprising more than one switch, which are not cross coupled · CPC title

• H03F2203/45494

  the CSC comprising one or more potentiometers · CPC title

• H03F1/42

  Modifications of amplifiers to extend the bandwidth · CPC title

• H03G5/28

  having semiconductor devices · CPC title

• H03F3/45654

  Controlling the active amplifying circuit of the differential amplifier · CPC title