Information processing device, control method of information processing device and control program of information processing device

Patent metadata

Field	Value
Publication number	US-2016019150-A1
Application number	US-201514712950-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	Jul 18, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

An information processing device comprising a plurality of nodes, each nodes comprising an arithmetic operation device configured to execute an arithmetic process, and a main memory which stores data, wherein each of arithmetic operation devices belonging to each of the plurality of nodes is configured to read a target data of which the arithmetic operation unit executes the arithmetic operation from a storage device except the main memory, based on a first address information indicating a storage position in the storage device, and write the target data into the main memory of own node.

First claim

What is claimed is:

1 . An information processing device comprising a plurality of nodes, each nodes comprising:
an arithmetic operation device configured to execute an arithmetic process; and a main memory which stores data, wherein each of arithmetic operation devices belonging to each of the plurality of nodes is configured to read a target data of which the arithmetic operation unit executes the arithmetic operation from a storage device except the main memory, based on a first address information indicating a storage position in the storage device, and write the target data into the main memory of own node.

2 . The information processing device according to claim 1 , wherein the arithmetic operation device is configured to write the target data into the main memory of own node, based on a second address information indicating a domain of the main memory belonging to each of the plurality of nodes.

3 . The information processing device according to claim 2 , wherein any one of the arithmetic operation device is configured to specify a write position of the target data in the main memory based on the second address information, and to write the target data into a specified write position in the main memory of own node.

4 . The information processing device according to claim 1 , wherein the arithmetic operation device is configured to write a result data of the arithmetic process into the main memory of the own node, and to write the result data which is written in the main memory of the own node into the storage device.

5 . The information processing device according to claim 4 , wherein the arithmetic operation device is configured to read the result data which is written in the main memory of the own node and write the result data which is read into the storage device, based on a third address information indicating a storage position of the result data in the main memory of other node.

6 . The information processing device according to claim 5 , wherein any one of the arithmetic operation device is configured to specify a write position of the result data in the main memory based on the second address information indicating a domain of the main memory belonging to each of the plurality of nodes, and to write the result data from a specified domain in the storage device.

7 . The information processing device according to claim 1 , wherein the arithmetic operation device is configured to read and write for executing a parallel arithmetic processing as the arithmetic process.

8 . A method of controlling an information processing device comprising a plurality of nodes, each nodes comprising an arithmetic operation device configured to execute an arithmetic process, and a main memory which stores data,
wherein the method comprising:
reading, by the arithmetic operation device, a target data of which an arithmetic operation unit in the arithmetic operation device belonging to each of the plurality of nodes executes the arithmetic operation from a storage device except the main memory, based on a address information indicating a storage position in the storage device;
writing, by the arithmetic operation device, the target data into the main memory of own node; and
executing, by the arithmetic operation device, the arithmetic process using the target data which is written into the main memory of own node.

9 . A non-transitory computer readable storage medium storing therein a program for causing an information processing device comprising a plurality of nodes, each nodes comprising an arithmetic operation device configured to execute an arithmetic processing, and a main memory which stores data to execute a process, the process comprising:
reading, by the arithmetic operation device, a target data of which an arithmetic operation unit in the arithmetic operation device belonging to each of the plurality of nodes executes the arithmetic operation from a storage device except the main memory, based on a address information indicating a storage position in the storage device; writing, by the arithmetic operation device, the target data into the main memory of own node; and executing, by the arithmetic operation device, the arithmetic process using the target data which is written into the main memory of own node.

Assignees

• Fujitsu Ltd

Inventors

• Otawa Tomohito

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/2542

  Non-uniform memory access [NUMA] architecture · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/0873

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F9/543

  User-generated data transfer, e.g. clipboards, dynamic data exchange [DDE], object linking and embedding [OLE] · CPC title