Method, Apparatus, and Chip for Implementing Mutually-Exclusive Operation of Multiple Threads

Patent metadata

Field	Value
Publication number	US-2016019100-A1
Application number	US-201514872946-A
Country	US
Kind code	A1
Filing date	Oct 1, 2015
Priority date	Apr 1, 2013
Publication date	Jan 21, 2016
Grant date	—

Abstract

Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

First claim

What is claimed is:

1 . A method, comprising:
receiving a lock message sent by a small core, wherein the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address corresponding to the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to a lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message.

2 . The method according to claim 1 , wherein calculating the code number of a lock assembly to which the requested lock belongs, comprises:
calculating a remainder by dividing the memory address corresponding to the requested lock by a quantity of lock assemblies of a computer node, and using the remainder as the code number of the lock assembly to which the requested lock belongs.

3 . The method according to claim 1 , wherein:
information about the requested lock comprises the memory address corresponding to the requested lock, a state of the requested lock, a quantity and code numbers of threads waiting for the requested lock, a code number of a thread currently using the requested lock, and information indicating a next thread to acquire the requested lock; the state of the requested lock is an idle state or an occupied state; and the sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message, comprises:
locating the information about the requested lock according to the memory address corresponding to the requested lock that is carried in the lock message;
sending the lock message to the lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message according to the information about the requested lock; and
updating the information about the requested lock.

4 . The method according to claim 1 , wherein:
information about the requested lock comprises the memory address corresponding to the requested lock, a state of the requested lock, a quantity of threads waiting for the requested lock, a code number of a thread currently using the requested lock, a vector indicating states of threads on a chip, and information indicating a next thread to acquire the requested lock; the states of the threads on a chip comprise the thread is waiting for the requested lock or the thread is not waiting for the requested lock; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message, comprises:
locating the information about the requested lock according to the memory address corresponding to the requested lock that is carried in the lock message;
sending the lock message to the lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message according to the information about the requested lock; and
updating the information about the requested lock.

5 . An apparatus, comprising:
a receiver, configured to receive a lock message sent by a small core, wherein the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for calculating, using the memory address corresponding to the requested lock, a code number of a lock assembly to which the requested lock belongs; and a transmitter, configured to transmit the lock message to the lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message.

6 . The apparatus according to claim 5 , wherein calculating the code number of a lock assembly to which the requested lock belongs, comprises:
calculating a remainder by dividing the memory address corresponding to the requested lock by a quantity of all lock assemblies of the apparatus, and using the remainder as the code number of the lock assembly to which the requested lock belongs.

7 . The apparatus according to claim 5 , wherein:
information about the requested lock comprises the memory address corresponding to the requested lock, a state of the requested lock, a quantity of and code numbers of threads waiting for the requested lock, a code number of a thread currently using the requested lock, and information indicating a next thread to acquire the requested lock, a state of the requested lock is an idle state or an occupied state; and transmitting the lock message to the lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message, comprises:
finding the information about the requested lock according to the memory address corresponding to the requested lock that is carried in the lock message;
transmitting the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message according to the information about the requested lock; and
updating the information about the requested lock.

8 . The apparatus according to claim 5 , wherein,
information about the requested lock comprises the memory address corresponding to the requested lock, a state of the requested lock, a quantity of threads waiting for the requested lock, a code number of a thread currently using the requested lock, a vector indicating states of threads on a chip, and information indicating a next thread to acquire the requested lock, the states of the threads comprise the thread is waiting for the requested lock and the thread is not waiting for the requested lock; and transmitting the lock message to the lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message, comprises:
locating the information about the requested lock according to the memory address corresponding to the requested lock that is carried in the lock message;
transmitting the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message according to the information about the requested lock; and
updating the information about the requested lock.

9 . A chip, comprising:
a small core; a routing component, configured to:
receive a lock message sent by the small core, wherein the lock message carries a memory address corresponding to a lock requested by a first thread in the small core;
calculate, using the memory address corresponding to the requested lock, a code number of a lock assembly to which the requested lock belongs; and
transmit the lock message to the lock assembly corresponding to the calculated code number, to request the lock assembly to process the lock message; and
the lock assembly, configured to receive a lock message from the routing component and process the lock message.

10 . The chip according to claim 9 , wherein calculating the code number of a lock assembly to which the requested lock belongs, comprises:
calculating a remainder by dividing the memory address corresponding to the requested lock by a quantity of lock assemblies of the chip, and using the remainder as the code number of the lock assembly to which the requested lock belongs.

11 . The chip according to claim 9 , wherein:
information about the requested lock comprises the memory address corresponding to the requested lock, a state of the requested lock, a quantity of and code numbers of threads waiting for the requested lock, a code number of a thread currently using the requested lock, and information indicating a

Assignees

• Huawei Tech Co Ltd

Inventors

• Xu Weizhi
• Tang Zhimin
• Zhang Zhimin
• Song Fenglong

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F12/1466 Primary

  Key-lock mechanism · CPC title

• G06F9/526 Primary

  Mutual exclusion algorithms · CPC title