Devices and techniques for integrated optical data communication

US2016013867A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016013867-A1
Application numberUS-201314436613-A
CountryUS
Kind codeA1
Filing dateFeb 15, 2013
Priority dateOct 19, 2012
Publication dateJan 14, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Devices and techniques for integrated optical data communication. A method of encoding symbols in an optical signal may include encoding a first symbol by injecting charge carriers, at a first rate, into a semiconductor device, such as a PIN diode. The method may also include encoding a second symbol by injecting charge carriers, at a second rate, into the semiconductor device. The first rate may exceed the second rate. A modulator driver circuit may include a resistive circuit coupled between supply terminal and drive terminals. The modulator driver circuit may also include a control circuit coupled between a data terminal and the resistive circuit. The control circuit may modulate a resistance of the resistive circuit by selectively coupling one or more of a plurality of portions of the resistive circuit to the drive terminal based on data to be optically encoded. In some embodiments, a modulator driver circuit and an optical modulator may be integrated on the same die or stacked (3D integrated) die and connected with through-oxide or through-silicon vias.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of encoding a first symbol and a second symbol in an optical signal carried by a waveguide, an optical property of the waveguide depending on a concentration of charge carriers in a portion of a semiconductor device, the method comprising: encoding the first symbol in the optical signal, wherein encoding the first symbol includes injecting charge carriers, at a first rate, into the portion of the semiconductor device; and encoding the second symbol in the optical signal, wherein encoding the second symbol includes injecting charge carriers, at a second rate, into the portion of the semiconductor device, wherein the first rate is greater than the second rate. 2 . The method of claim 1 , wherein injecting charge carriers at the first rate comprises applying a forward bias voltage to the semiconductor device while controlling a drive strength of the semiconductor device, the forward bias voltage exceeding a threshold voltage of the semiconductor device. 3 . The method of claim 1 wherein injecting charge carriers at the second rate comprises applying a forward bias voltage to the semiconductor device while controlling a drive strength of the semiconductor device, the forward bias voltage not exceeding a threshold voltage of the semiconductor device. 4 . The method of claim 1 , wherein: encoding the first symbol further comprises performing pre-emphasis of charge carrier injection by injecting charge carriers, at a third rate, into the portion of the semiconductor device, prior to injecting charge carriers at the first rate, and the third rate is greater than the first rate. 5 . The method of claim 4 , wherein injecting charge carriers at the third rate comprises applying a forward bias voltage to the semiconductor device while controlling a drive strength of the semiconductor device, the forward bias voltage exceeding a threshold voltage of the semiconductor device, wherein the drive strength of the semiconductor device during injection of charge carriers at the third rate exceeds the drive strength of the semiconductor device during injection of charge carriers at the first rate. 6 . The method of claim 1 wherein encoding the second symbol further comprises depleting charge carriers from the portion of the semiconductor device prior to injecting the charge carriers at the second rate. 7 . The method of claim 6 , wherein depleting charge carriers from the portion of the semiconductor device comprises applying a reverse bias voltage to the semiconductor device. 8 . The method of claim 1 wherein: the semiconductor device is a PIN diode, and the portion of the semiconductor device is an intrinsic region of the PIN diode. 9 . An integrated circuit for controlling an optical modulator, the optical modulator configured to encode data in an optical signal carried by an optical waveguide, the optical modulator including a semiconductor device, an optical property of the waveguide depending on a concentration of charge carriers in a portion of a semiconductor device, the integrated circuit comprising: a modulator driver circuit configured: to control encoding of a first symbol in the optical signal by injecting charge carriers into a portion of the semiconductor device at a first rate, and to control encoding of a second symbol in the optical signal by injecting charge carriers into the portion of the semiconductor device at a second rate, wherein the first rate is greater than the second rate. 10 . The integrated circuit of claim 9 , wherein the modulator driver circuit is configured to inject charge carriers at the first rate by applying a forward bias voltage to the semiconductor device while providing a first signal to the semiconductor device, the forward bias voltage exceeding a threshold voltage of the semiconductor device. 11 . The integrated circuit of claim 9 , wherein the modulator driver circuit is configured to inject charge carriers at the second rate by applying a forward bias voltage to the semiconductor device, the forward bias voltage not exceeding a threshold voltage of the semiconductor device. 12 . The integrated circuit of claim 9 , wherein: the modulator driver circuit is further configured to encode the first symbol by pre-emphasizing injection of charge carrier injection, pre-emphasizing injection of charge carriers comprises injecting charge carriers, at a third rate, into the portion of the semiconductor device, prior to injecting charge carriers at the first rate, and the third rate is greater than the first rate. 13 . The integrated circuit of claim 12 , wherein the modulator driver circuit is configured to inject charge carriers at the third rate by applying a forward bias voltage to the semiconductor device while providing a second signal to the semiconductor device, the forward bias voltage exceeding a threshold voltage of the semiconductor device, wherein a drive strength of the second signal exceeds a drive strength of the first signal. 14 . The integrated circuit of claim 9 , wherein the modulator driver circuit is further configured to encode the second symbol by depleting charge carriers from the portion of the semiconductor device prior to injecting the charge carriers at the second rate. 15 . The integrated circuit of claim 14 , wherein the driver modulator circuit is configured to deplete charge carriers from the portion of the semiconductor device by applying a reverse bias voltage to the semiconductor device. 16 . The integrated circuit of claim 9 , wherein: the semiconductor device is a PIN diode, and the portion of the semiconductor device is an intrinsic region of the PIN diode. 17 . The integrated circuit of claim 9 , further comprising the optical modulator and the optical waveguide. 18 . The integrated circuit of claim 9 , wherein the integrated circuit is a monolithic integrated circuit fabricated in a standard CMOS process. 19 . A method of fabricating an integrated circuit in a manufacturing process, comprising: in a first layer of the manufacturing process, fabricating a body of a transistor of a modulator driver circuit configured to control an optical modulator, the transistor being configured to modulate a resistance between an optical modulator and a supply; in a second layer of the manufacturing process, fabricating a gate of the transistors of the modulator driver circuit; and fabricating an optical waveguide core in the first layer and/or the second layer of the manufacturing process. 20 . The method of claim 19 , further comprising fabricating a diode in the first layer of the manufacturing process, wherein a portion of the optical waveguide core is embedded in a portion of the diode. 21 . The method of claim 19 , wherein the manufacturing process is a standard CMOS process. 22 . The method of claim 19 , wherein the manufacturing process is a 65 nm process, a 45 nm process, a 32 nm process, a 28 nm process, a 22 nm process, a 14 nm process, an 11 nm process, a 7 nm process, or a 5 nm process. 23 . The method of claim 19 , wherein the manufacturing process is a sub-90 nm process. 24 . An integrated circuit for controlling an optical modulator, the optical modulator configured to encode data in an optical signal carried by an optical waveguide, the optical modulator including a semiconductor device, an optical property of the waveguide depending on a concentration of charge carriers in a portio

Assignees

Inventors

Classifications

  • H04B10/516Primary

    Details of coding or modulation · CPC title

  • Operation of devices; Circuit arrangements, not otherwise provided for in this subclass · CPC title

  • in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence) · CPC title

  • Circuits for the control or stabilisation of the bias voltage, e.g. automatic bias control [ABC] feedback loops · CPC title

  • involving resonance effects, e.g. resonantly enhanced interaction · CPC title

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What does patent US2016013867A1 cover?
Devices and techniques for integrated optical data communication. A method of encoding symbols in an optical signal may include encoding a first symbol by injecting charge carriers, at a first rate, into a semiconductor device, such as a PIN diode. The method may also include encoding a second symbol by injecting charge carriers, at a second rate, into the semiconductor device. The first rate m…
Who is the assignee on this patent?
Massachusetts Inst Technology
What technology area does this patent fall under?
Primary CPC classification H04B10/516. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).