Low leakage dual sti integrated circuit including fdsoi transistors

Patent metadata

Field	Value
Publication number	US-2016013206-A1
Application number	US-201314771016-A
Country	US
Kind code	A1
Filing date	Feb 28, 2013
Priority date	Feb 28, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

First claim

1 - 14 . (canceled)

15 . An integrated circuit, comprising:
a UTBOX type insulator layer; a first cell, comprising:
first and second FDSOI field effect transistors located above the UTBOX layer;
a first shallow trench isolation separating the first and second transistors;
a first semiconductor ground plane having a first type of doping and located beneath the first transistor and beneath the insulator layer;
a first semiconductor well extending continuously beneath the first and second transistors and contacting the first ground plane, the first well having a second type of doping different from the first type;
a second cell, comprising:
third and fourth FDSOI field effect transistors located above the UTBOX layer;
a second shallow trench isolation separating the third and fourth transistors;
a second semiconductor ground plane having the first type of doping and located beneath the third transistor and beneath the insulator layer;
a second semiconductor well extending continuously beneath the third and fourth transistors and contacting the second ground plane, the second well having the second type of doping;
a third shallow trench isolation separating the first and second cells, crossing the insulator layer and reaching the bottom of the first and second wells; a deep well having the first type of doping and extending continuously beneath the first and second wells, the deep well having a portion beneath the third shallow trench isolation whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second shallow trench isolations.

16 . An integrated circuit according to claim 15 , wherein the doping density of the portion of the deep well is at least 50% higher than the average doping density of the deep well.

17 . An integrated circuit according to claim 15 , wherein the portion extends at least 30 nm under the third shallow trench isolation.

18 . An integrated circuit according to claim 15 , wherein the portion extends into the bottom of the deep well.

19 . An integrated circuit according to claim 15 , wherein the distance between the portion and the bottom of the deep well is between 10 and 50 nm.

20 . An integrated circuit according to claim 15 , wherein the first type of doping is n type.

21 . An integrated circuit according to claim 15 , further comprising:
a biasing contact for the deep well; a fourth shallow trench isolation separating the biasing contact from the first and second cells, the deep well comprising a portion located beneath the fourth shallow trench isolation and whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second shallow trench isolations.

22 . An integrated circuit according to claim 15 , further comprising a biasing circuit programmed to bias the first and second wells with respective different voltages.

23 . A method for manufacturing an integrated circuit, comprising:
providing a stack including a semiconductor substrate, a UTBOX type insulator layer lying above the semiconductor substrate, and a semiconductor layer lying above the insulator layer; in the stack, forming first and second grooves; in the stack, forming a third groove, the third groove extending in the semiconductor substrate deeper than the first and second grooves and being located between the first and second grooves; doping a portion of the semiconductor substrate at the bottom of the third groove with a first type of doping; filling the first, second, and third grooves with insulation material to form first, second, and third shallow trench isolations respectively; doping part of the semiconductor substrate with the first type of doping to form a deep well extending deeper than the third shallow trench isolation and extending continuously below the first and second shallow trench isolations and contacting the doped portion, the doped portion having a doping density at least 50% higher than the doping density of the deep well beneath the first and second shallow trench isolations; doping part of the semiconductor substrate to form first and second wells on opposite sides of the third shallow trench isolation, the first and second wells having a second type of doping different from the first type and extending deeper than the bottom of the first and second shallow trench isolations, the third shallow trench isolation extending deeper than the bottom of the formed first and second wells; doping an upper portion of the first and second wells to form ground planes under the insulator layer, the formed ground planes having the first type of doping.

24 . A method according to claim 23 , further comprising:
forming first and second FDSOI field effect transistors separated by the first shallow trench isolation; forming third and fourth FDSOI field effect transistors separated by the second shallow trench isolation, respective source, drain, and channel of each of the first to fourth transistors being formed in the semiconductor layer.

25 . A method according to claim 23 , wherein the doping the portion of the semiconductor substrate includes ionic implantation in the bottom of the third groove.

26 . A method according to claim 23 , wherein the doping the portion of the semiconductor substrate is performed by plasma doping.

27 . A method according to claim 23 , wherein the doped portion extends at least 30 nm under the bottom of the third groove.

28 . A method according to claim 23 , wherein the bottom of the doped portion extends into the bottom of the formed deep well.

Assignees

• Commissariat Á L Énergie Atomique Et Aux Énergies Alternatives
• IBM
• St Microelectronics Inc
• Commissariat Energie Atomique

Inventors

• Vinet Maud
• Cheng Kangguo
• Doris Bruce
• Grenouillet Laurent
• Khakifirooz Ali
• Le Tiec Yannick
• Liu Qing

Classifications

• H10P32/1204

  from a plasma phase · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/0148

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title