One time programming memory cell, array structure and operating method thereof

Patent metadata

Field	Value
Publication number	US-2016013193-A1
Application number	US-201414515902-A
Country	US
Kind code	A1
Filing date	Oct 16, 2014
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a drain terminal. The gate terminal of the transistor is connected with a word line. The source terminal of the transistor is connected with a bit line. A first end of the first varactor is connected with the drain terminal of the transistor. A second end of the first varactor is connected with a first program line. A first end of the second varactor is connected with the drain terminal of the transistor. A second end of the second varactor is connected with a second program line.

First claim

What is claimed is:

1 . A one time programming memory cell, comprising:
a P-type substrate; a first gate structure disposed on a surface of the P-type substrate, and connected with a word line; a second gate structure disposed on the surface of the P-type substrate, and connected with a first program line; a third gate structure disposed on the surface of the P-type substrate, and connected with a second program line; a first N-type diffusion region disposed under the surface of the P-type substrate, located near a first side of the first gate structure, and connected with a bit line; and a second N-type diffusion region disposed under the surface of the P-type substrate, wherein the second N-type diffusion region is located near a second side of the first gate structure, wherein a channel region underlying the second gate structure is a first N-type doped channel region, and a channel region underlying the third gate structure is a second N-type doped channel region, wherein a first varactor is defined by the second gate structure, the first N-type doped channel region and the second N-type diffusion region collaboratively, wherein a second varactor is defined by the third gate structure, the second N-type doped channel region and the second N-type diffusion region collaboratively, wherein a transistor is defined by the first gate structure, the P-type substrate, the first N-type diffusion region and the second N-type diffusion region collaboratively.

2 . The one time programming memory cell as claimed in claim 1 , wherein the first gate structure comprises a gate oxide layer and a polysilicon gate connected with the word line, wherein the gate oxide layer is formed on the surface the P-type substrate, and the polysilicon gate is formed on the gate oxide layer.

3 . The one time programming memory cell as claimed in claim 1 , wherein the second gate structure comprises a gate oxide layer and a polysilicon gate connected with the first program line, wherein the gate oxide layer is formed on the surface the P-type substrate, and the polysilicon gate is formed on the gate oxide layer.

4 . The one time programming memory cell as claimed in claim 1 , wherein the third gate structure comprises a gate oxide layer and a polysilicon gate connected with the second program line, wherein the gate oxide layer is formed on the surface the P-type substrate, and the polysilicon gate is formed on the gate oxide layer.

5 . The one time programming memory cell as claimed in claim 3 , wherein when a first voltage is provided to the bit line, a second voltage is provided to the word line and a third voltage is provided to the first program line, the gate oxide layer of the second gate structure is ruptured, so that the first varactor is turned into a first resistor, wherein the third voltage is higher than the second voltage, and the second voltage is higher than the first voltage.

6 . The one time programming memory cell as claimed in claim 1 , wherein the first N-type doped channel region and the second N-type doped channel region are N-type extension regions, N-well regions or N-type doped regions.

7 . A one time programming memory cell, comprising:
a transistor having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the transistor is connected with a word line, and the source terminal of the transistor is connected with a bit line; a first varactor, wherein a first end of the first varactor is connected with the drain terminal of the transistor, and a second end of the first varactor is connected with a first program line; and a second varactor, wherein a first end of the second varactor is connected with the drain terminal of the transistor, and a second end of the second varactor is connected with a second program line.

8 . The one time programming memory cell as claimed in claim 7 , wherein the transistor comprises:
a first gate structure disposed on a surface of a P-type substrate, and connected with the word line; a first N-type diffusion region disposed under the surface of the P-type substrate, located near a first side of the first gate structure, and connected with the bit line; and a second N-type diffusion region disposed under the surface of the P-type substrate, wherein the second N-type diffusion region is located near a second side of the first gate structure.

9 . The one time programming memory cell as claimed in claim 7 , wherein the first varactor comprises:
a second gate structure disposed on the surface of the P-type substrate, and connected with the first program line; the second N-type diffusion region located near a first side of the second gate structure; and a first N-type doped channel region disposed under the second gate structure.

10 . The one time programming memory cell as claimed in claim 9 , wherein the second varactor comprises:
a third gate structure disposed on the surface of the P-type substrate, and connected with the second program line; the second N-type diffusion region located near a first side of the third gate structure; and a second N-type doped channel region disposed under the third gate structure.

11 . The one time programming memory cell as claimed in claim 10 , wherein the first N-type doped channel region and the second N-type doped channel region are N-type extension regions, N-well regions or N-type doped regions.

12 . The one time programming memory cell as claimed in claim 9 , wherein when a first voltage is provided to the bit line, a second voltage is provided to the word line and a third voltage is provided to the first program line, a gate oxide layer of the first varactor is ruptured, so that the first varactor is turned into a first resistor, wherein the third voltage is higher than the second voltage, and the second voltage is higher than the first voltage.

13 . The one time programming memory cell as claimed in claim 12 , wherein when a fourth voltage is provided to the bit line, a fifth voltage is provided to the word line, and a sixth voltage is provided to the first program line and the second program line, the bit line generates a read current, wherein the fifth voltage and the sixth voltage is higher than the fourth voltage.

14 . An array structure, comprising:
a first one time programming memory cell comprising:
a first transistor having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the first transistor is connected with a first word line, and the source terminal of the first transistor is connected with a first bit line;
a first varactor, wherein a first end of the first varactor is connected with the drain terminal of the first transistor, and a second end of the first varactor is connected with a first program line; and
a second varactor, wherein a first end of the second varactor is connected with the drain terminal of the first transistor, and a second end of the second varactor is connected with a second program line; and
a second one time programming memory cell comprising:
a second transistor having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the second transistor is connected with a second word line, and the source terminal of the second transistor is connected with the first bit line;
a third varactor, wherein a first end of the third varactor is connected with the drain terminal of the second transistor, and a second end of the third varactor is connected with the third program line; and
a fourth varactor, wherein a first end of the second varactor is connected with the drain terminal of the second transis

Assignees

• Ememory Technology Inc

Inventors

• Wu Meng-Yi
• Chen Hsin-Ming

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title