Passive component integrated with semiconductor device in semiconductor package

Patent metadata

Field	Value
Publication number	US-2016013169-A1
Application number	US-201514863774-A
Country	US
Kind code	A1
Filing date	Sep 24, 2015
Priority date	Feb 27, 2007
Publication date	Jan 14, 2016
Grant date	—

Abstract

According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

First claim

1 - 20 . (canceled)

21 . A semiconductor package comprising:
a substrate having lower and upper surfaces; at least one passive component coupled to first and second conductive pads and situated on said upper surface of said substrate; at least one semiconductor device being directly coupled to said lower surface of said substrate, and being electrically coupled to said at least one passive component; said at least one semiconductor device having a first electrode for electrical and mechanical connection to a conductive pad external to and not disposed on said semiconductor package.

22 . The semiconductor package of claim 21 , wherein said at least one semiconductor device has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.

23 . The semiconductor package of claim 22 , wherein said at least one semiconductor device has a third electrode adjacent to said first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package.

24 . The semiconductor package of claim 22 , wherein said first and second electrodes of said at least one semiconductor device are situated on opposing surfaces of said at least one semiconductor device.

25 . The semiconductor package of claim 21 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate and having a plurality of input/output electrodes.

26 . The semiconductor package of claim 25 , wherein each of said input/output electrodes is electrically and mechanically coupled to one of a plurality of conductive pads on said upper surface of said substrate.

27 . The semiconductor package of claim 25 further comprising a second conductive pad on said lower surface of said substrate, wherein said second conductive pad on said lower surface of said substrate is coupled to one of said plurality of input/output electrodes of said IC die.

28 . The semiconductor package of claim 21 , wherein said at least one passive component is electrically and mechanically coupled to each of said first and second conductive pads by a conductive adhesive.

29 . The semiconductor package of claim 22 , wherein said at least one semiconductor device is a FET, wherein said first electrode is a source electrode of said FET and said second electrode is a drain electrode of said FET.

30 . The semiconductor package of claim 21 , wherein said at least one semiconductor device is a GaN device.

31 . A semiconductor package comprising:
a substrate having lower and upper surfaces; a passive component situated on said upper surface of said substrate; a power transistor being coupled to said lower surface of said substrate through a first conductive pad; said passive component being electrically coupled to said power transistor in said semiconductor package.

32 . The semiconductor package of claim 31 , wherein said power transistor has a first electrode for electrical and mechanical connection to a second conductive pad external to said semiconductor package.

33 . The semiconductor package of claim 32 , wherein said power transistor has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.

34 . The semiconductor package of claim 31 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate.

35 . The semiconductor package of claim 31 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate and electrically connected to said power transistor.

36 . The semiconductor package of claim 35 , wherein said IC die comprises a controller for controlling said power transistor.

37 . The semiconductor package of claim 31 , wherein said passive component comprises a bypass capacitor.

38 . The semiconductor package of claim 31 , wherein said passive component comprises an output capacitor.

39 . The semiconductor package of claim 31 , wherein said power transistor is a GaN device.

Assignees

• Int Rectifier Corp

Inventors

• Standing Martin

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title