Light emitting device reflective bank structure

Patent metadata

Field	Value
Publication number	US-2016013167-A1
Application number	US-201514864570-A
Country	US
Kind code	A1
Filing date	Sep 24, 2015
Priority date	Dec 10, 2012
Publication date	Jan 14, 2016
Grant date	—

Abstract

Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.

First claim

What is claimed is:

1 . A light emitting diode bank structure comprising:
a substrate; an insulating layer on the substrate; an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls; and a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting device includes a micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers; and a passivation layer spanning sidewalls of the array of vertical light emitting diode device and least partially filling the array of bank openings.

2 . The light emitting diode bank structure of claim 1 , wherein each vertical light emitting diode device has a maximum width of 1 μm-100 μm, and the micro p-n diode includes one or more layers based on II-VI materials or III-V materials.

3 . The light emitting diode bank structure of claim 2 , wherein a top surface of each vertical light emitting diode device is above a top surface of the insulating layer.

4 . The light emitting diode bank structure of claim 2 , wherein each vertical light emitting diode device comprises a top conductive electrode and a bottom conductive electrode.

5 . The light emitting diode bank structure of claim 4 , wherein no vertical light emitting diode device spans along a sidewall of a corresponding bank opening.

6 . The light emitting diode bank structure of claim 2 ,
wherein each vertical light emitting diode device comprises a top conductive electrode and a bottom conductive electrode; and wherein the passivation layer does not completely cover the top conductive electrode of each vertical light emitting diode device.

7 . The light emitting diode bank structure of claim 6 , further comprising a transparent conductor layer over and in electrical contact with the top conductive electrode for each vertical light emitting diode device.

8 . The light emitting diode bank structure of claim 7 , wherein the passivation layer is transparent the visible wavelength spectrum.

9 . The light emitting diode bank structure of claim 8 , further comprising a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer.

10 . The light emitting diode bank structure of claim 9 , wherein the reflective layer completely covers the sidewalls of each of the bank openings.

11 . The light emitting diode bank structure of claim 9 , wherein the reflective layer completely covers the bottom surface of each of the bank openings.

12 . The light emitting diode bank structure of claim 9 , wherein the passivation layer covers the reflecting layer that spans the sidewalls of each of the bank openings in the insulating layer.

13 . The light emitting diode bank structure of claim 4 , further comprising:
one or more integrated circuits interconnected with the bottom conductive electrodes of each vertical light emitting diode device; and an electrical line out on the insulating layer and in electrical contact with the top conductive electrode of each vertical light emitting diode device.

14 . The light emitting diode bank structure of claim 13 , further comprising a transparent conductor layer over and in electrical contact with the electrical line out and the top conductive electrode of each vertical light emitting diode device.

15 . The light emitting diode bank structure of claim 4 , further comprising:
one or more integrated circuits interconnected with the bottom conductive electrodes of each vertical light emitting diode device; a via opening in the insulating layer; and an electrical line out beneath the via opening and in electrical contact with the top conductive electrode of each vertical light emitting diode device.

16 . The light emitting diode bank structure of claim 15 , further comprising a transparent conductor layer over and in electrical contact with the electrical line out and the top conductive electrode of each vertical light emitting diode device.

17 . The light emitting diode bank structure of claim 4 , further comprising:
one or more integrated circuits interconnected with the bottom conductive electrodes of each vertical light emitting diode device; and an array of electrical lines out on the insulating layer, the array of electrical lines out in electrical contact with the top conductive electrodes of the array of vertical light emitting diode devices.

18 . The light emitting diode bank structure of claim 17 , further comprising an array of transparent conductor layers, each transparent conductor layer over and in electrical contact with a corresponding electrical line out and a top conductive electrode of a corresponding vertical light emitting diode device.

19 . The light emitting diode bank structure of claim 4 , further comprising:
one or more integrated circuits interconnected with the bottom conductive electrodes of each vertical light emitting diode device; an array of via openings in the insulating layer; and an array of electrical lines out beneath each of the corresponding array of via openings, the array of electrical lines out in electrical contact with the top conductive electrodes of the array of vertical light emitting diode devices.

20 . The light emitting diode bank structure of claim 19 , further comprising an array of transparent conductor layers, each transparent conductor layer over and in electrical contact with a corresponding electrical line out and a top conductive electrode of a corresponding vertical light emitting diode device.

Assignees

• Luxvue Technology Corp

Inventors

• Sakariya Kapil V
• Bibl Andreas
• Hu Hsin-Hua

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title