Semiconductor device and method for forming the same

US2016013094A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016013094-A1
Application numberUS-201514864726-A
CountryUS
Kind codeA1
Filing dateSep 24, 2015
Priority dateJun 13, 2013
Publication dateJan 14, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. The semiconductor device also includes a plurality of buried gates formed over the active region, and a barrier film formed between neighboring buried gates from the plurality of buried gates.

First claim

Opening claim text (preview).

1 - 6 . (canceled) 7 . A method for forming a semiconductor device comprising: forming a device isolation film for defining an active region over a semiconductor substrate; forming a plurality of buried gates over the active region; and forming a barrier film between neighboring buried gates from the plurality of buried gates. 8 . The method according to claim 7 , wherein the forming the device isolation film includes: forming a trench for forming the device isolation film in the semiconductor substrate; forming a liner insulation film along a surface of the trench; and forming the device isolation film over the liner insulation film by filling a remaining portion of the trench with an insulation material. 9 . The method according to claim 8 , wherein the forming the barrier film includes: exposing a sidewall of a lower portion of the active region by forming a hole in the device isolation film; and forming the barrier film by oxidizing the exposed sidewall of the lower portion of the active region. 10 . The method according to claim 9 , further comprising: when the hole is formed, removing the liner insulation film of the sidewall of the lower portion of the active region while the liner insulation film of a sidewall of an upper portion of the active region remains. 11 . The method according to claim 8 , wherein the forming the barrier film includes: exposing a sidewall of a lower portion of the active region by forming a hole in the device isolation film; and forming an air-gap-shaped barrier film by selectively etching the lower portion of the exposed active region. 12 . The method according to claim 11 , wherein: when the hole is formed, the liner insulation film of the sidewall of the lower portion of the active region is removed while the liner insulation film of a sidewall of an upper portion of the active region remains; and when the air-gap-shaped barrier film is formed, the lower portion of the active region is etched using the liner insulation film of the sidewall of the upper portion of the active region as a mask. 13 . The method according to claim 11 , further comprising: after completion of the selective etching, forming an oxide film at a top surface and a bottom surface of the barrier film by oxidizing the exposed part of the active region. 14 . The method according to claim 11 , further comprising: filling the hole with an insulation material. 15 . A method for forming a semiconductor device comprising: defining an active region comprising an ion implantation region in a semiconductor substrate; forming a first insulation film along a surface of the active region, and forming a second insulation film along a circumference of the ion implantation region; and forming a buried gate at both sides of the ion implantation region in the active region, and wherein the ion implantation region has a first oxidation rate and the semiconductor substrate has a second oxidation rate. 16 . The method according to claim 15 , wherein the defining the active region includes: forming the ion implantation region by implanting ions into the semiconductor substrate; and forming a device isolation region by etching the semiconductor substrate in such a manner that the ion implantation region is contained in the active region. 17 . The method according to claim 15 , wherein the defining the active region includes: forming a device isolation region by etching the semiconductor substrate, thereby also defining the active region; and forming the ion implantation region by implanting ions into the active region. 18 . The method according to claim 16 , further comprising: partially exposing a sidewall of the ion implantation region during the formation of the device isolation region. 19 . The method according to claim 18 , wherein the second insulation film is formed by oxidation through the exposed sidewall of the ion implantation region. 20 . The method according to claim 15 , wherein the first insulation film and the second insulation film comprise oxide films and are simultaneously formed. 21 . The method according to claim 15 , wherein a top surface of the ion implantation region is higher in height than a bottom surface of the buried gate. 22 . The method according to claim 15 , wherein the second oxidation rate is higher than the first oxidation rate.

Assignees

Inventors

Classifications

  • of insulating materials · CPC title

  • into Group IV semiconductors · CPC title

  • of electrically active species · CPC title

  • the regions having non-rectangular shapes, e.g. rounded (H10W10/0123 takes precedence) · CPC title

  • formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

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What does patent US2016013094A1 cover?
A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. The semiconductor device also includes a plurality of buried gates formed over the active region, and a barrier film formed between neighboring buried…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W10/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).