Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016013092-A1
Application number	US-201514796984-A
Country	US
Kind code	A1
Filing date	Jul 10, 2015
Priority date	Jul 10, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

After embedding a silicon oxide film within a second trench that opens in a semiconductor substrate using a silicon nitride film as a hard mask, the silicon oxide film over the silicon nitride film is polished, and then, wet etching is performed before a step for removing the silicon nitride film, and thereby the upper surface of the silicon oxide film within a first trench opened in the silicon nitride film is retreated.

First claim

What is claimed is:

1 . A method for manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate; (b) forming a first insulation film over the semiconductor substrate, the first insulation film including an opening that exposes a part of the semiconductor substrate; (c) forming a trench in the upper surface of the semiconductor substrate by performing etching using the first insulation film as a mask; (d) embedding a second insulation film in the inside of the trench by forming the second insulation film over the semiconductor substrate; (e) flattening the upper surface of the second insulation film by polishing the second insulation film over the first insulation film; (f) after the step (e), retreating the upper surface of the second insulation film by performing etching; and (g) after the step (f), removing the first insulation film.

2 . The method for manufacturing a semiconductor device according to claim 1 ,
wherein etching performed in the step (f) is wet etching.

3 . The method for manufacturing a semiconductor device according to claim 1 ,
wherein, when the first insulation film is removed in the step (g), the height of the upper surface of the second insulation film is higher than the height of the upper surface of the semiconductor substrate.

4 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of:
(h) after the step (g), retreating the surface of the second insulation film by performing wet etching.

5 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of:
(i) after the step (d) and before the step (e), covering the second insulation film right above the trench by a resist film, using the resist film as a mask, and retreating the upper surface of the second insulation film over the first insulation film.

6 . The method for manufacturing a semiconductor device according to claim 1 ,
wherein the film thickness of the first insulation film formed in the step (b) is 200 nm or more.

7 . The method for manufacturing a semiconductor device according to claim 1 ,
wherein the first insulation film is a silicon nitride film, and the second insulation film is a silicon oxide film.

8 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of:
(j) after the step (b) and before the step (c), forming a third insulation film between the end of the first insulation film and the semiconductor substrate by performing oxidation treatment.

9 . The method for manufacturing a semiconductor device according to claim 1 ,
wherein the upper surface of the first insulation film is not polished and the upper surface of the first insulation film is covered by the second insulation film even after polishing in the step (e), and wherein the second insulation film covering the upper surface of the first insulation film is removed in the step (f), and thereby the upper surface of the first insulation film is exposed.

Assignees

• Renesas Electronics Corp

Inventors

• Aika Tomohiko
• Suzuki Hajime
• Fujita Naoki

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title