Display panel, displayer and driving method

Patent metadata

Field	Value
Publication number	US-2016012792-A1
Application number	US-201414547427-A
Country	US
Kind code	A1
Filing date	Nov 19, 2014
Priority date	Jul 11, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

The present invention discloses a display panel, a displayer and the drive method thereof, the display panel comprising a cell substrate and an array substrate. The array substrate comprises a plurality of gate lines and a plurality of data lines, wherein, a sub-pixel unit is defined by an i-th line gate line, an (i+1)-th line gate line, a j-th column data line and aj+1-th column data line, wherein, i and j are both natural number. The outermost side of the cell substrate is provided with an FPR film array comprising a first FPR film and a second FPR film, wherein, the first FPR film is corresponding to the first pixel electrode so as to convert emitting light of the first pixel electrode into polarized light in a first direction, and the second FPR film is corresponding to the second pixel electrode so as to convert emitting light of the second pixel electrode into polarized light in a second direction, wherein, the first direction is different from the second direction. The displayer shows the original images as well as the interference image at the same time, thereby the original image shown in the displayer cannot be seen and the display information in displayer is protected effectively.

First claim

What is claimed is:

1 . A display panel, comprising:
an array substrate including a plurality of gate lines and a plurality of data lines, wherein, a sub-pixel unit is defined by an i-th line gate line, an (i+1)-th line gate line, a j-th column data line and a (j+1)-th column data line, wherein, i and j are both natural number, the sub-pixel unit comprising:
a first TFT, a gate of the first TFT being electrically connected to the (i+1)-th line gate line, a source of the first TFT being electrically connected to the j-th column date line, and a drain of the first TFT being electrically connected to a first pixel electrode by a first via;
a first pixel electrode for controlling display of an original image; and
a second pixel electrode for controlling display of an interference image; and
a cell substrate, the outermost side of the cell substrate being provided with an FPR film array, the FPR film array comprising:
a first FPR film corresponding to the first pixel electrode so as to convert emitting light of the first pixel electrode into polarized light in a first direction; and
a second FPR film corresponding to the second pixel electrode so as to convert emitting light of the second pixel electrode into polarized light in a second direction, wherein, the first direction is different from the second direction.

2 . The display panel according to claim 1 , wherein, the first direction is substantially opposite to the second direction.

3 . The display panel according to claim 1 , wherein, the sub-pixel unit further comprising a second TFT, a gate of the second TFT being electrically connected to the i-th line gate line, a source of the second TFT being electrically connected to the (j+1)-th column date line, and a drain of the second TFT being electrically connected to the second pixel electrode by a second via.

4 . The display panel according to claim 1 , wherein, the second pixel electrodes in a plurality of sub-pixel units are interconnected, extend to a non-display area and are connected with a control switch, a high level signal or a low level signal being input into the second pixel electrode by the control switch so as to control the second pixel electrode to display interference image.

5 . The display panel according to claim 1 , wherein, the first pixel electrode and the second pixel electrode are disposed in parallel, or the first pixel electrode is fully surrounded by the second pixel electrode, or the first pixel electrode is partially surrounded by the second pixel electrode.

6 . The display panel according to claim 1 , wherein, the cell substrate is a color filter substrate comprising a color filter, a substrate provided on the color filter, and an upper polarizing filter provided on the substrate, and the FPR film array is attached on the upper polarizing filter.

7 . The display panel according to claim 6 , wherein, the color filter substrate comprises a transparent portion provided in the same layer as that of the color filter, the color filter being corresponding to the first pixel electrode, and the transparent portion being corresponding to the second pixel electrode.

8 . The display panel according to claim 1 , wherein, the display panel is a liquid crystal display panel or an organic light-emitting diode display panel.

9 . A displayer, comprising the display panel according to claim 1 .

10 . The displayer according to claim 9 , further comprising a signal process device comprising:
a system board configured to input the date signal of the original image; a image process unit configured to mix the date signal of the interference image and the data signal of the original image so as to output a mixed signal; and a time-controller configured to process the mixed signal and then output source driving signal to a source driver IC and gate driving signal to a gate driver IC, respectively.

11 . The displayer according to claim 10 , wherein, the image process unit is further configured to:
perform an anti-color process of the date signal of the original image, and serve the acquired data signal of the anti-color image of the original image as the data signal of the interference image; and perform an interlace superposition of the date signal of the original image and the date signal of the anti-color image according to pixel lines to acquire a mixed signal and then output the mixed signal to the time-controller.

12 . The displayer according to claim 10 , wherein, the image process unit is further configured to perform an interlace superposition of the date signal of the original image and the date signal of the interference image according to the pixel lines to acquire a mixed signal and then output the mixed signal to the time-controller, wherein, the gray value of the interference image is set as the largest gray value.

13 . The displayer according to claim 9 , wherein, the first direction is substantially opposite to the second direction.

14 . The displayer according to claim 9 , wherein, the sub-pixel unit further comprising a second TFT, a gate of the second TFT being electrically connected to the i-th line gate line, a source of the second TFT being electrically connected to the (j+1)-th column date line, and a drain of the second TFT being electrically connected to the second pixel electrode by a second via.

15 . The displayer according to claim 9 , wherein, the second pixel electrodes in a plurality of sub-pixel units are interconnected, extend to a non-display area and are connected with a control switch, a high level signal or a low level signal being input into the second pixel electrode by the control switch so as to control the second pixel electrode to display interference image.

16 . The displayer according to claim 9 , wherein, the first pixel electrode and the second pixel electrode are disposed in parallel, or the first pixel electrode is fully surrounded by the second pixel electrode, or the first pixel electrode is partially surrounded by the second pixel electrode.

17 . The displayer according to claim 9 , wherein, the cell substrate is a color filter substrate comprising a color filter, a substrate provided on the color filter, and an upper polarizing filter provided on the substrate, and the FPR film array is attached on the upper polarizing filter.

18 . The displayer according to claim 17 , wherein, the color filter substrate comprises a transparent portion provided in the same layer as that of the color filter, the color filter being corresponding to the first pixel electrode, and the transparent portion being corresponding to the second pixel electrode.

19 . A drive method for an array substrate in a display panel, the array substrate including a plurality of gate lines and a plurality data lines, wherein, a sub-pixel unit is defined by an i-th line gate line, an (i+1)-th line gate line, a j-th column data line and a (j+1)-th column data line, wherein, i and j are both natural number, the sub-pixel unit comprising:
a first TFT, a gate of the first TFT being electrically connected to the (i+1)-th line gate line, a source of the first TFT being electrically connected to the j-th column date line, and a drain of the first TFT being electrically connected to a first pixel electrode by a first via; a first pixel electrode for controlling display of original image; and a second pixel electrode for controlling display of interference image; the method comprising the following steps: by a image process unit, acquiring original image of each frame from a system bo

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Pan
• Li Wenbo

Classifications

• G02F1/13363

  Birefringent elements, e.g. for optical compensation · CPC title

• G09G2358/00

  Arrangements for display data security · CPC title

• G09G2300/0443

  with several sub-pixels for the same colour in a pixel, not specifically used to display gradations (G09G3/364 takes precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title