Solid state memory command queue in hybrid device

Patent metadata

Field	Value
Publication number	US-2016011966-A1
Application number	US-201314066266-A
Country	US
Kind code	A1
Filing date	Oct 29, 2013
Priority date	Oct 29, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

Systems and methods are disclosed for improving performance in of storage device latency. In an embodiment, an apparatus may comprise a controller configured to receive a first data access command at a device including a nonvolatile solid state memory and a disc memory, and when the first data access command is directed to the nonvolatile solid state memory, store the first data access command to a first command queue for the nonvolatile solid state memory. In another embodiment, a method may comprise receiving, at a data storage device, a first data access command, storing the first data access command in a first command queue, determining whether the data access command is directed to a Flash memory or a disc memory, and storing the first data access command in a second command queue when the first data access command is directed to the Flash memory.

First claim

2 - 3 . (canceled)

4 . The apparatus of claim 1 further comprising:
the first controller further configured to:
after storing the first data access command to the second command queue, send an indication that the first data access command has been received and that additional commands may be sent to the first controller.

5 . The apparatus of claim 1 further comprising:
the first controller further configured to:
receive a second data access command directed to the first nonvolatile solid state memory before execution of the first data access command has completed; and
store the second data access command to the second command queue.

6 . The apparatus of claim 5 further comprising:
the first controller further configured to:
store a third data access command to the second command queue;

the solid state memory controller further configured to:
determine if both the second data access command and the third data access command can be performed with a single data access; and
perform the single data access based on the determination.

7 . The apparatus of claim 1 further comprising:
an interface configured to receive commands from the host device; and
the first controller further configured to return results of commands to the host device over the interface.

8 . The apparatus of claim 1 further comprising:
the first nonvolatile solid state memory is a NAND Flash memory; and
the second nonvolatile memory is a disc memory.

9 . The apparatus of claim 1 further comprising:
a data access command is directed to the first nonvolatile solid state memory when the data access command requests data stored in the first nonvolatile solid state memory or when the data access command includes data to be written to the first nonvolatile solid state memory.

10 . A memory device storing instructions that cause a processor to perform a method comprising:
receiving a first data access command at a data storage device including a first nonvolatile memory and a cache memory; storing the first data access command to a first command queue; determining which of the first nonvolatile memory and the cache memory the first data access command is directed to and when the first data access command is directed to the cache memory, storing the first data access command to a second command queue configured to store data access commands directed to the cache memory before the data access commands reach a controller for the cache memory.

11 . (canceled)

12 . The memory device of claim 10 , the method further comprising:
after storing the first data access command to the second command queue, sending an indication that the first data access command has been received and that additional commands may be sent to the controller.

13 . The memory device of claim 10 , the method further comprising:
beginning execution of the first data access command; receiving a second data access command directed to the cache memory before execution of the first data access command has completed; and storing the second data access command to the second first command queue.

14 . The memory device of claim 13 , the method further comprising:
storing a third data access command to the second first command queue; determining if both the second data access command and the third data access command will require accessing a same data entity of the cache memory, a data entity being an amount of storage space accessed during a single access operation; and when both the second data access command and the third data access command require accessing the same data entity, perform a single access operation for both the second data access command and the third data access command.

15 . The memory device of claim 10 , the method further comprising:
receiving the first data access command from a host device over an interface; and returning results of commands to the host device over the interface.

16 . An apparatus comprising:
a data storage controller configured to:
receive a first data access command from a first command queue;
determine which of a Flash memory and a first nonvolatile memory having a slower access time than the Flash memory the first data access command is directed to; and
when the first data access command is directed to the Flash memory, store the first data access command in a second command queue before the first data access command reaches a Flash controller for the Flash memory.

17 . The apparatus of claim 16 further comprising:
the data storage controller further configured to:
send an indication that the first data access command was received successfully after storing the first data access command in the second command queue;
receive and store a second data access command to the second command queue before the first data access command has finished executing; and

the Flash controller, the Flash controller configured to being execution of the first data access command prior to the second data access command being stored to the second command queue.

18 . The apparatus of claim 17 further comprising:
the data storage controller further configured to:
store a third data access command to the second command queue;

the Flash controller further configured to:
determine if the second data access command and the third data access command can be completed with a single data access operation to the Flash memory; and
perform the single data access operation to resolve the second data access command and the third data access command when both can be completed with the single data access operation.

19 . The apparatus of claim 18 further comprising:
the data storage controller further configured to store an intermediate data access command to the second command queue between the second data access command and the third data access command.

20 . The apparatus of claim 16 further comprising:
the Flash controller further configured to:
perform a plurality of data access operations stored in the second command queue on the Flash memory in an order based on a priority value associated with each of the plurality of data access operations.

21 . The apparatus of claim 1 further comprising:
the solid state memory controller further configured to perform a plurality of read or write data access operations stored in the second command queue on the first nonvolatile solid state memory based on a priority value associated with each of the plurality of data access operations.

22 . The memory device of claim 10 , the method further comprising:
performing, on the cache memory, a plurality of read or write data access operations stored in the second command queue in an order based on a priority value associated with each of the plurality of data access operations.

23 . The apparatus of claim 1 further comprising:
the first command queue and the second command queue include volatile random access memory; and
the second command queue is physically separate from the solid state memory controller.

Assignees

• Seagate Technology Llc

Inventors

• Keeler Stanton Macdonough
• Lapanse Margot Ann

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/217

  Hybrid disk, e.g. using both magnetic and solid state storage devices · CPC title

• G06F2212/225

  Hybrid cache memory, e.g. having both volatile and non-volatile portions · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F12/10

  Address translation · CPC title