Undefined instruction recoding

Patent metadata

Field	Value
Publication number	US-2016011875-A1
Application number	US-201414325981-A
Country	US
Kind code	A1
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A system and method for efficiently decoding and handling undefined instructions. A semiconductor chip predecodes instructions of a computer program. In response to determining a particular instruction is an undefined operation, the chip replaces an N-bit opcode in the particular instruction with an N-bit pattern different from the opcode. When instructions are fetched from an instruction cache, the corresponding opcodes are compared to the N-bit pattern. When a match is found, a trap may be set. The trap may later cause an exception handler subroutine for undefined operations to initiate execution.

First claim

What is claimed is:

1 . A processor comprising:
an instruction cache (i-cache) configured to store a plurality of instructions; and control logic configured to:
receive a first instruction;
in response to determining that the first instruction corresponds to an undefined operation, replace an opcode of the first instruction with one or more bits different from the opcode; and
store the first instruction with the replaced opcode in the i-cache.

2 . The processor as recited in claim 1 , wherein an indication the first instruction stored in the i-cache is an undefined operation is represented by the one or more bits different from the opcode within the first instruction.

3 . The processor as recited in claim 1 , wherein the control logic is further configured to:
fetch a second instruction from the i-cache; and determine if an opcode of a second instruction corresponds to an undefined operation.

4 . The processor as recited in claim 3 , wherein determining the opcode of the second instruction corresponds to an undefined operation comprises determining the opcode of the second instructions matches the one or more bits.

5 . The processor as recited in claim 1 , wherein the one or more bits consist of a number of bits that varies in dependence on a size of the opcode.

6 . The processor as recited in claim 1 , wherein to determine the first instruction corresponds to an undefined operation, the control logic is configured to determine the opcode of the first instruction corresponds to an operation to be performed by a coprocessor that is disabled.

7 . The processor as recited in claim 2 , wherein to determine the first instruction corresponds to an undefined operation, the control logic is configured to determine the opcode of the first instruction corresponds to an operation that writes to a read-only register or read-only region of memory.

8 . A method comprising:
receiving a first instruction; in response to determining that the first instruction corresponds to an undefined operation, replacing an opcode of the first instruction with one or more bits different from the opcode; and storing the first instruction with the replaced opcode in an instruction cache (i-cache).

9 . The method as recited in claim 8 , wherein an indication the first instruction stored in the i-cache is an undefined operation is represented by the one or more bits different from the opcode within the first instruction.

10 . The method as recited in claim 9 , further comprising:
fetching a second instruction from the i-cache; and determining if an opcode of a second instruction corresponds to an undefined operation.

11 . The method as recited in claim 10 , wherein determining the opcode of the second instruction corresponds to an undefined operation comprises determining the opcode of the second instruction matches the one or more bits.

12 . The method as recited in claim 8 , wherein the one or more bits consist of a number of bits that varies in dependence on a size of the opcode.

13 . The method as recited in claim 8 , wherein to determine the first instruction corresponds to an undefined operation, the method comprises determining the opcode of the first instruction corresponds to an operation to be performed by a coprocessor that is disabled.

14 . The method as recited in claim 9 , wherein to determine the first instruction corresponds to an undefined operation, the method comprises determining the opcode of the first instruction corresponds to an operation that writes to a read-only register or read-only region of memory.

15 . The method as recited in claim 8 , wherein one or more bits comprise a predetermined pattern.

16 . The method as recited in claim 15 , wherein the predetermined pattern is programmable.

17 . A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:
receive a first instruction; in response to determining that the first instruction corresponds to an undefined operation, replace an opcode of the first instruction with one or more bits different from the opcode; and store the first instruction with the replaced opcode in an instruction cache (i-cache).

18 . The non-transitory computer readable storage medium as recited in claim 15 , wherein an indication the first instruction stored in the i-cache is an undefined operation is represented by the one or more bits different from the opcode within the first instruction.

19 . The non-transitory computer readable storage medium as recited in claim 16 , wherein the program instructions are further executable to:
fetch a second instruction from the i-cache; and determine if an opcode of a second instruction corresponds to one or more bits which indicate an undefined operation.

20 . The non-transitory computer readable storage medium as recited in claim 17 , wherein determining the opcode of the second instruction corresponds to an undefined operation comprises determining the opcode of the second instruction matches the one or more bits.

Assignees

• Apple Inc

Inventors

• Sundar Shyam

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/3808 Primary

  for instruction reuse, e.g. trace cache, branch target cache · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F9/3812

  with instruction modification, e.g. store into instruction stream · CPC title