Protection and recovery from sudden power failure in non-volatile memory devices

Patent metadata

Field	Value
Publication number	US-2016011806-A1
Application number	US-201414523979-A
Country	US
Kind code	A1
Filing date	Oct 27, 2014
Priority date	Jul 13, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.

First claim

1 . A method for data storage, comprising:
for a memory comprising groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell; initially storing data in the memory using the normal mode; and in response to an event, reverting to the protected mode for at least one of the groups of the memory cells.

2 . The method according to claim 1 , further comprising:
defining at least a first programming operation that stores first data in a given group of the memory cells by writing to the memory cells respective analog values representing respective bit values of the first data; and defining at least a second programming operation that stores in the given group second data in addition to the first data by modifying the respective analog values of the memory cells in the given group so as to represent bit value combinations of the first and second data, such that, at all times during execution of the second programming operation in the protected mode, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

3 . The method according to claim 2 , wherein storing the data comprises configuring the first programming operation to program the memory cells with normal analog values when operating in the normal mode, and to program the memory cells with protected analog values, different from the normal analog values, when operating in the protected mode.

4 . The method according to claim 3 , wherein reverting to the protected mode comprises identifying one or more groups of the memory cells that have been programmed only with the first data, and modifying the analog values in the memory cells of the identified groups from the normal analog values to the protected analog values.

5 . The method according to claim 1 , further comprising:
reading the data from the groups that are programmed in the normal mode using first read thresholds; and reading the data from the groups that are programmed in the protected mode using second read thresholds that are different from the first read thresholds.

6 . The method according to claim 1 , wherein the event comprises reception of a flush command.

7 . The method according to claim 6 , further comprising acknowledging the flush command only after reverting to the protected mode.

8 . A data storage apparatus, comprising:
a memory comprising groups of memory cells; and a processor, which is configured to define a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell, to initially store data in the memory using the normal mode, and, in response to an event, to revert to the protected mode for at least one of the groups of the memory cells.

9 . The apparatus according to claim 8 , wherein the processor is configured to:
define at least a first programming operation that stores first data in a given group of the memory cells by writing to the memory cells respective analog values representing respective bit values of the first data; and define a second programming operation that stores in the given group second data in addition to the first data by modifying the respective analog values of the memory cells in the given group so as to represent bit value combinations of the first and second data,
wherein, at all times during execution of the second programming operation in the protected mode, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

10 . The apparatus according to claim 9 , wherein the processor is configured to configure the first programming operation so as to program the memory cells with normal analog values when operating in the normal mode, and with protected analog values, different from the normal analog values, when operating in the protected mode.

11 . The apparatus according to claim 10 , wherein the processor is configured to identify one or more groups of the memory cells that have been programmed only with the first data, and to modify the analog values in the memory cells of the identified groups from the normal analog values to the protected analog values.

12 . The apparatus according to claim 8 , wherein the processor is configured to read the data from the groups that are programmed in the normal mode using first read thresholds, and to read the data from the groups that are programmed in the protected mode using second read thresholds that are different from the first read thresholds.

13 . The apparatus according to claim 8 , wherein the event comprises reception of a flush command.

14 . The apparatus according to claim 13 , wherein the processor is configured to acknowledge the flush command only after reverting to the protected mode.

15 . A system, comprising:
a host; and a storage device, comprising:
a memory comprising groups of memory cells; and
a processor configured to define a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell, to initially store data in the memory using the normal mode, and, in response to an event, to revert to the protected mode for at least one of the groups of the memory cells.

16 . The system according to claim 15 , wherein the processor is configured to:
define at least a first programming operation that stores first data in a given group of the memory cells by writing to the memory cells respective analog values representing respective bit values of the first data; and define a second programming operation that stores in the given group second data in addition to the first data by modifying the respective analog values of the memory cells in the given group so as to represent bit value combinations of the first and second data,
wherein, at all times during execution of the second programming operation in the protected mode, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

17 . The system according to claim 16 , wherein the processor is configured to configure the first programming operation so as to program the memory cells with normal analog values when operating in the normal mode, and with protected analog values, different from the normal analog values, when operating in the protected mode.

18 . The system according to claim 17 , wherein the processor is configured to identify one or more groups of the memory cells that have been programmed only with the first data, and to modify the analog values in the memory cells of the identified groups from the normal analog values to the protected analog values.

19 . The system according to claim 15 , wherein the processor is configured to read the data from the groups that are programmed in the normal mode using first read thresholds, and to read the data from the groups that are programmed in the protected mode using second read thresholds that are different from the first read thresholds.

20 . The system according to claim 15 , wherein the event comprises reception of a flush command from the h

Assignees

• Apple Inc

Inventors

• Zaltsman Etai
• Meir Avraham Poza

Classifications

• G11C27/005

  with non-volatile charge storage, e.g. on floating gate or MNOS · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G11C16/225

  Preventing erasure, programming or reading when power supply voltages are outside the required ranges · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title