Digital filter with a pipeline structure, and a corresponding device

Patent metadata

Field	Value
Publication number	US-2016011625-A1
Application number	US-201514730408-A
Country	US
Kind code	A1
Filing date	Jun 4, 2015
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.

First claim

1 . A digital filter, comprising:
a pipeline structure including a plurality of processing structures each timed by a respective clock signal, wherein each processing structure includes plural processing modules for processing input samples, a phase generator configured to align said processing modules to said input samples so that each said input sample is processed by a respective one of the processing modules in said processing structures, up-sampling and down-sampling buffers configured to be activated when said processing structures operate at different clock frequencies, a first clock domain, and a second clock domain, said up-sampling and down-sampling buffers configured to convert signal samples between said first clock domain and said second clock domain.

2 . The filter of claim 1 , wherein said phase generator is a centralized phase generator configured to distribute a phase alignment signal across the processing modules of said processing structures.

3 . The filter of claim 1 , wherein said phase generator is a distributed phase generator, each processing module being provided with a dedicated phase alignment signal to be fed to a subsequent processing module along with the serialized data in the pipeline.

4 . The filter of any claim 1 , further including a clock generator configured to deliver a higher clock frequency of said different clock frequencies to manage serial processing of said input samples.

5 . The filter of claim 1 , wherein said filter is a IIR filter.

6 . The filter of claim 1 , implemented as a digital signal processor.

7 . A filter, comprising:
a first processing structure operating in accordance with a first clock and including a plurality of first processing modules arranged in a first rotating processing scheme timed by said first clock; a second processing structure operating in accordance with a second clock, wherein the second clock has a lower frequency than the first clock, and including a plurality of second processing modules arranged in a second rotating processing scheme timed by said second clock; a down-sampling buffer configured to receive first input data at the first clock and output first output data at the second clock for processing through the second processing structure; and an up-sampling buffer configured to receive second input data output from the second processing structure at the second clock and output second output data at the first clock.

8 . The filter of claim 7 , wherein the first input data is derived from data output from the first processing structure.

9 . The filter of claim 7 , wherein data input to the first processing structure is derived from the second output data.

10 . The filter of claim 7 , further comprising a phase generator configured to align said first and second processing modules to data samples so that each input sample is processed by a respective one of the first and second processing modules.

11 . The filter of claim 10 , wherein said phase generator is a centralized phase generator configured to distribute a phase alignment signal across the processing modules of said processing structures.

12 . The filter of claim 10 , wherein said phase generator is a distributed phase generator, each processing module being provided with a dedicated phase alignment signal to be fed to a subsequent processing module.

13 . The filter of claim 7 , wherein the first and second processing structures are arranged in a pipeline structure.

14 . The filter of claim 7 , wherein said filter is a IIR filter.

15 . The filter of claim 7 , implemented as a digital signal processor.

Assignees

• St Microelectronics Srl

Inventors

• Pirozzi Francesco

Classifications

• H03H17/0292 Primary

  Time multiplexed filters; Time sharing filters · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• H03H2220/04

  Pipelined · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title