Multilayer ceramic capacitor with interposer, and interposer for multilayer ceramic capacitor

US2016007446A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016007446-A1
Application numberUS-201414768424-A
CountryUS
Kind codeA1
Filing dateFeb 12, 2014
Priority dateFeb 18, 2013
Publication dateJan 7, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An embodiment of an multilayer ceramic capacitor with interposer includes: an interposer 20 having an insulated substrate 21 , two first conductor pads 22 , two second conductor pads 23 and two conductor vias 24 connecting the first conductor pads 22 and second conductor pads 23 ; and a multilayer ceramic capacitor 10 having external electrodes 12 that are each connected to each first conductor pad 22 of the interposer 20 via solder SOL. Each conductor via 24 of the interposer 20 has a through hole 24 a inside, and a void GA not filled with the solder SOL is present in each through hole 24 a on the second conductor pad 23 side. The multilayer ceramic capacitor with interposer is capable of suppressing noise due to electrostriction.

First claim

Opening claim text (preview).

1 . A multilayer ceramic capacitor with interposer comprising a multilayer ceramic capacitor and an interposer installed on it, wherein: (1) the multilayer ceramic capacitor is structured in such a way that it has: a dielectric chip of roughly rectangular solid shape that houses multiple internal electrode layers stacked in a manner not contacting each other; and two external electrodes each provided on one of opposite end faces of the dielectric chip in a manner partially covering four side faces adjoining the end face and where an area partially covering the four side faces has four side faces of roughly rectangular shape; wherein ends of some of the multiple internal electrode layers are connected to one of the two external electrodes, while ends of the others are connected to the other of the two external electrodes; (2) the interposer is structured in such a way that it has: an insulated substrate of roughly rectangular sheet shape; two first conductor pads of roughly rectangular shape provided on one side of the insulated substrate in its thickness direction in a manner each facing one side face of roughly rectangular shape of each of the two external electrodes; two second conductor pads provided on the other side of the insulated substrate in its thickness direction in a manner facing the two first conductor pads, respectively; and one or more one-side conductor vias provided on the insulated substrate in a manner penetrating through it in its thickness direction, at a location(s) on an inner side of an outer edge of one of the two first conductor pads and of an outer edge of one of the two second conductor pads, as well as one or more other-side conductor vias provided on the insulated substrate in a manner penetrating through it in its thickness direction, at a location(s) on an inner side of an outer edge of the other of the two first conductor pads and of an outer edge of the other of the two second conductor pads; wherein one of the two first conductor pads is connected to one of the two second conductor pads via the one or more one-side conductor vias, while the other of the two first conductor pads is connected to the other of the two second conductor pads via the one or more other-side conductor vias; (3) the two first conductor pads of the interposer each have joined to its surface, via solder, one side face of roughly rectangular shape of each of the two external electrodes of the multilayer ceramic capacitor; (4) the one or more one-side conductor vias each have a through hole inside that opens at a surface of one of the two first conductor pads and at a surface of one of the two second conductor pads, while the one or more other-side conductor vias each have a through hole inside that opens at a surface of the other of the two first conductor pads and at a surface of the other of the two second conductor pads; and (5) voids not filled with the solder are present in the through hole(s) of the one or more one-side conductor vias on the surface side of one of the two second conductor pads, and also in the through hole(s) of the one or more other-side conductor vias on the surface side of the other of the two second conductor pads. 2 . A multilayer ceramic capacitor with interposer according to claim 1 , wherein, when a direction specifying an outermost end distance between the two first conductor pads of the interposer represents a length direction, then the outermost end distance between the two first conductor pads and a length of the insulated substrate have a dimensional relationship of “Outermost end distance≦Insulated substrate length.” 3 . A multilayer ceramic capacitor with interposer according to claim 1 , wherein an outermost end distance between the two first conductor pads of the interposer and an end face distance between the two external electrodes of the multilayer ceramic capacitor have a dimensional relationship of “Outermost end distance≦External electrode end face distance.” 4 . A multilayer ceramic capacitor with interposer according to claim 1 , wherein, when a direction specifying an outermost end distance between the two second conductor pads of the interposer represents a length direction, then the outermost end distance between the two second conductor pads and a length of the insulated substrate have a dimensional relationship of “Outermost end distance≦Insulated substrate length.” 5 . An interposer for a multilayer ceramic capacitor used for mounting the multilayer ceramic capacitor on a substrate, etc., wherein: (1) the multilayer ceramic capacitor is structured in such a way that it has: a dielectric chip of roughly rectangular solid shape that houses multiple internal electrode layers stacked in a manner not contacting each other; and two external electrodes each provided on one of opposite end faces of the dielectric chip in a manner partially covering four side faces adjoining the end face and where an area partially covering the four side faces has four side faces of roughly rectangular shape; wherein ends of some of the multiple internal electrode layers are connected to one of the two external electrodes, while ends of the others are connected to the other of the two external electrodes; (2) the interposer is structured in such a way that it has: an insulated substrate of roughly rectangular sheet shape; two first conductor pads of roughly rectangular shape provided on one side of the insulated substrate in its thickness direction in a manner each facing one side face of roughly rectangular shape of each of the two external electrodes; two second conductor pads provided on the other side of the insulated substrate in its thickness direction in a manner facing the two first conductor pads, respectively; and one or more one-side conductor vias provided in a manner penetrating through the insulated substrate in its thickness direction, on an inner side of an outer edge of one of the two first conductor pads and of an outer edge of one of the two second conductor pads, as well as one or more other-side conductor vias provided in a manner penetrating through the insulated substrate in its thickness direction, on an inner side of an outer edge of the other of the two first conductor pads and of an outer edge of the other of the two second conductor pads; wherein one of the two first conductor pads is connected to one of the two second conductor pads via the one or more one-side conductor vias, while the other of the two first conductor pads is connected to the other of the two second conductor pads via the one or more other-side conductor vias; (3) the two first conductor pads of the interposer are each used to join, via solder, one side face of roughly rectangular shape of each of the two external electrodes of the multilayer ceramic capacitor; and (4) the one or more one-side conductor vias each have a through hole inside that opens at a surface of one of the two first conductor pads and at a surface of one of the two second conductor pads, while the one or more other-side conductor vias each have a through hole inside that opens at a surface of the other of the two first conductor pads and at a surface of the other of the two second conductor pads. 6 . An interposer for a multilayer ceramic capacitor according to claim 5 , wherein, when a direction specifying an outermost end distance between the two first conductor pads of the interposer represents a length direction, then the outermost end distance between the two first conductor pads and a length of the insulated substrate have a dimensional relationship of “Outermost end distance≦Insulated substrate length.” 7 . An interposer for a multilayer ceramic capacitor according to claim 5 , wherein an outermost end distance between the two first conductor pads of the interposer and an end face distance between the two e

Assignees

Inventors

Classifications

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Via provided in pad; Pad over filled via · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

  • H05K1/0216Primary

    Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

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What does patent US2016007446A1 cover?
An embodiment of an multilayer ceramic capacitor with interposer includes: an interposer 20 having an insulated substrate 21 , two first conductor pads 22 , two second conductor pads 23 and two conductor vias 24 connecting the first conductor pads 22 and second conductor pads 23 ; and a multilayer ceramic capacitor 10 having external electrodes 12 that are each connected to each …
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).